The Pulse
Microsoft’s Wavel Targets Wafer-Scale AI’s Compiler Bottleneck
Microsoft Research’s Wavel compiler builds executable schedules for wafer-scale accelerators, addressing decisions about physical placement, layout and execution order. The paper reports throughput and speedup gains on WSE-3 hardware, along
AI.info Team · Written with AI ·
Wafer-scale accelerators put vast computing resources on a single chip, but existing compilers still leave key decisions about where operations run and in what order unresolved. Microsoft Research’s Wavel takes a different approach: build the physical execution schedule directly, rather than treating the job mainly as dividing a model into logical shards. Microsoft Research lists September 4, 2026, as the paper’s publication date. The work is listed among the publications for ACM SOSP 2026, held September 29–October 2.
“We make a key observation: at wafer scale, the central complexity of compilation shifts from finding a logical shard plan to constructing an executable schedule that fixes placement, layout alignment, and execution ordering.”
The authors of Wavel write in their paper.
Why shard plans leave decisions open
In conventional compilation, a system can first decide how to split a model across processors, then map those pieces onto hardware. Wavel’s authors argue that approach misses a defining feature of wafer-scale accelerators: communication costs vary sharply with physical location, while the possible placements and execution schedules multiply quickly.
A logical partition therefore does not settle how a workload should run. The compiler must also choose where each operation sits, align layouts across the device and set the order of execution. Those physical choices affect communication and throughput, and the paper frames them as the central compilation challenge.
MeshIR makes the schedule explicit
Wavel represents executable schedules in an intermediate representation called MeshIR. It builds schedules using two locality-preserving operations, CUT and TUNE, then evaluates candidates with a physical cost model. Structured pruning narrows the search, an important design choice when the number of possible mappings would otherwise make exhaustive exploration impractical.
The approach shifts the compiler’s output from a high-level distribution plan toward a concrete account of how computation will occupy the wafer. The publication summary does not describe Wavel as a new accelerator or a replacement for model-serving software; its contribution is the compilation system that maps workloads to wafer-scale hardware.
Measured gains and a modeled MoE result
On WSE-3 hardware, Microsoft says Wavel achieved 1.31 to 1.35 times higher mean throughput per setting than expert-optimized WaferLLM. For dense models, the team reports up to a 1.85-times speedup over the Full-Chip baseline.
The paper also gives a 2.97-times speedup for mixture-of-experts workloads against that same baseline, but marks the figure as a prediction from calibrated cost-model results. It is not reported as a measured hardware result. That distinction matters: the dense-model comparisons are hardware results, while the MoE number estimates performance through the model.
A compiler claim, not a hardware claim
Wavel’s results put compiler decisions—not a new chip design—at the center of the performance comparison. The reported advantage over WaferLLM is relative to expert-optimized settings, and the larger MoE figure remains predictive. Microsoft lists the paper among its ACM SOSP 2026 publications; the conference took place in Prague from September 29 to October 2.
The work’s concrete claim is that wafer-scale systems need compilers to reason directly about physical placement, layout and execution order. Its WSE-3 measurements show gains over the stated baselines; the MoE projection has not been established by the same kind of hardware measurement.