The Pulse
Architect Labs’ AI Chip Still Needs Silicon to Prove Itself
Architect Labs says its AI system designed and verified the Redwood inference accelerator in under two weeks from a specification written by two human architects. Redwood currently runs on an FPGA, while the company projects stronger perfor
AI.info Team ·
Architect Labs says its artificial intelligence system designed, verified and deployed a working inference accelerator in less than two weeks. The result, called Redwood, runs on an FPGA today; the company’s larger claim depends on whether the design survives fabrication and post-silicon testing.
The announcement, published by Architect Labs on August 27, describes a process that began with a high-level specification written by two human architects. From there, the company says its Architect Labs Platform generated the performance model, RTL hardware description, UVM verification environments, formal proofs, firmware, drivers and custom compute kernels without human intervention below the specification.
“Redwood was not designed in a traditional chip design process,” Architect Labs writes in its announcement. The company says it replaced sequential handoffs between architecture, hardware, verification and software with a single optimization loop.
Redwood Starts With an FPGA, Not a Wafer
Redwood Nano, a scaled-down version of the accelerator, currently runs on an AMD Versal FPGA at 250 megahertz. Architect Labs says it executes single-batch inference on open-weight models including Qwen and Llama, with live demonstrations shown at this year’s Design Automation Conference.
The company reports a measured throughput of 12.1 tokens per second for Qwen3-0.6B on the FPGA. That figure is not a fabricated-chip result, and it does not establish that Redwood outperforms Nvidia hardware in its present form.
Architect Labs instead projects the design onto a Samsung 8-nanometer process comparable to the technology used by Nvidia’s Jetson Orin Nano. Under that projection, Redwood Nano would reach 49 tokens per second against 28 tokens per second measured on the Jetson, while drawing 1.335 watts instead of 2.59 watts. The company estimates a 3.4-fold improvement in performance per watt and an NPU area of 2.88 square millimeters.
Those figures remain estimates. Architect Labs’ technical paper describes the comparison as a projection onto silicon, while the measured Redwood result comes from the FPGA implementation.
Two Architects Set the Target
Redwood uses a tile-based spatial-dataflow architecture aimed at low-power, low-latency inference for physical AI workloads. Each tile combines a RISC-V control core with matrix and vector compute engines, sharing 512 kilobytes of local memory. A custom on-chip network connects the tiles and uses direct data movement rather than repeatedly routing work through shared memory.
The design separates control logic from compute. Architect Labs says the control side can run at a slower clock rate or shut down during kernel execution, while the compiler manages prefetching, double buffering and out-of-order computation. External memory traffic passes through modular DMA engines built around standard AXI4 interfaces, allowing the compute fabric to be integrated into a larger system or used as a chiplet.
The company says the system generated every RTL block, verification environment, formal artifact, firmware component and kernel from the human-written specification. It also reports that each block through the system-on-chip level achieved at least 95% code and functional coverage using commercial electronic-design-automation tools, an internal formal engine and hardware-in-the-loop validation.
Architect Labs further says the first RTL design moved from simulation to the FPGA platform without deployment bugs. A separate emulation environment reduced optimization runs from roughly 15 hours to between 15 and 30 minutes, allowing the system to test more architectural options than a small human team could examine in the same period.
The Company Claims a Closed Design Loop
Architect Labs’ software does not stop at generating hardware descriptions. The company says it co-developed the firmware, kernels and performance models alongside the hardware, then used functional, area, timing and power feedback to regenerate designs when the specification changed.
According to the company, every architectural iteration returned to the FPGA in under 48 hours. The process lets human architects adjust the specification rather than manually repair each downstream artifact, keeping hardware and software changes tied to the same design target.
The approach also produced a limited feedback loop between the accelerator and the system that built it. Architect Labs deployed Qwen3 on Redwood, exposed the model as an endpoint inside its design platform and used repeated sampling to identify timing changes and kernel optimizations for later versions of the accelerator.
The company describes that experiment as an early form of recursive self-improvement, but the claim has a narrow meaning here. A model running on the accelerator helped identify optimizations for a future accelerator generation; the system did not independently define its own goals or redesign the entire platform without human direction.
TSMC Tapeout Is the Test That Matters
Architect Labs says it is developing Redwood toward full GDSII and a tapeout at TSMC. That step will expose problems an FPGA cannot fully represent, including manufacturing variation, physical timing, power delivery, thermal behavior and the gap between projected and actual area.
The company’s own announcement acknowledges that “real silicon is the final ground truth.” Until Redwood reaches a manufactured chip, its comparison with the Jetson Orin Nano remains a combination of FPGA measurements and process-based estimates.
The distinction matters because chip design claims often fail at the transition from logical correctness to physical implementation. Verification coverage can show that a design behaves as intended across tested conditions, but it does not eliminate the manufacturing and packaging risks that appear after tapeout.
Architect Labs’ public demonstration is still significant for a different reason. The company has shown an automated flow that moves from a written specification to a functioning FPGA implementation, including hardware, verification and software, in a compressed period. The next milestone is not another benchmark: it is whether Redwood returns from a foundry as a working chip.