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Sr. Staff Engineer, CPU (Front-End) Verification

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software

In inglese

Company

Tenstorrent

Location

Austin, Texas, United States; Santa Clara, California, United States

Status

Open

Posted

2026-09-04T12:40:39+00:00

Tenstorrent is hiring a design verification engineer for unit-level verification of its RISC-V CPU front end: instruction fetch, branch prediction and fetch control. Work includes UVM testbenches, constrained-random and directed stimulus for misspeculation and redirect flows, C++ reference models, and coverage closure, alongside RTL designers. The posting asks for prior front-end block verification using SystemVerilog, UVM and C++, plus reusable testbench design. It is hybrid from Austin or Santa Clara, uses open-source flows such as Verilator, and offers depend on U.S. export-control eligibility; the posted level may be adjusted.