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RTL Design Engineer – Interconnect & Network Datapath

About the TeamOpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native si

In inglese

Company

OpenAI

Location

San Francisco

Status

Open

Posted

2026-06-23T23:52:56.682+00:00

OpenAI's Hardware organization is hiring a senior RTL engineer to own on-chip fabric and off-chip interconnect for a custom AI accelerator. The work covers microarchitecture and SystemVerilog implementation of NoC fabrics, switches, routers, bridges, arbiters, queues and schedulers, plus routing, flow control, congestion management and QoS, through verification closure, physical design convergence, tape-out and silicon bring-up. The posting wants recent hands-on production RTL ownership of packet-switched datapaths such as Ethernet switches, NICs/SmartNICs, RDMA/RoCE or NoCs, and expects mentoring of junior engineers and third-party IP engagements.