VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing

AI summary

Overview

• Research area: Multi-Agent Systems applied to electronic design automation (EDA) — specifically, using vision-language models and collaborative agents to size analog and mixed-signal (AMS) integrated circuits. The paper appears in the workshop track "AI for Chip Design" (arXiv:2601.07315v5 [cs.MA]).
• Technical level: Advanced. Readers need familiarity with analog circuit design trade-offs (gain, phase margin, unity-gain bandwidth, THD, offset, power), Bayesian optimization terminology, and multimodal language model agents.
• Scope: The paper presents VLM-CAD, a five-stage agentic workflow that parses circuit schematics into symbolic graphs, reasons over schematic plus netlist with specialist language-model agents, performs DC operating-point and full-specification sizing, and finishes with an explainable trust-region Bayesian optimizer that produces sensitivity evidence for a final design report.

What This Paper Is About

Automatically choosing transistor sizes for analog circuits is hard because the design space is high-dimensional and full of trade-offs among power, performance and area. Existing automated methods read only textual netlists, which discard the global topological and spatial context that a circuit schematic gives a human expert, while vision-language models that could read schematics suffer from spatial blindness and logical hallucinations on dense diagrams. VLM-CAD addresses this by combining a neuro-symbolic schematic parser (Image2Net) that converts raw pixels into explicit topology graphs and structured JSON, a team of specialist language-model agents that reason step by step from DC biasing to full-spec optimization, and an explainable optimizer (ExTuRBO) that reports quantified sensitivity evidence for the final design.

Key Contributions

1. VLM-CAD, a VLM-optimized collaborative agent workflow for analog circuit sizing that follows the step-by-step multimodal reasoning process of expert designers, deducing latent constraints and performing hierarchical reasoning from DC biasing to full-specification optimization. The workflow has five stages: (A) neuro-symbolic schematic parsing via Image2Net, (B) cross-modal circuit netlist and specifications analysis, (C) DC-OP sizing, (D) inference-only sizing, and (E) ExTuRBO sizing and explaining.

2. Image2Net integration as a neuro-symbolic structural parsing module that anchors VLM reasoning in deterministic facts. It finetunes a YOLOv8-Pose model on a training set of 2,268 noise-free circuit schematics from prior work, uses deterministic feature detection plus Density-Based Spatial Clustering of Applications with Noise (DBSCAN) for corner detection, builds a connectivity graph using vectorized array slicing for orthogonal connections and Bresenham's algorithm for diagonal paths, and emits an annotated color-coded schematic plus a structured JSON description that serves as explicit, topology-grounded visual memory.

3. ExTuRBO, an Explainable Trust Region Bayesian Optimization method with two features: Collaborative Semantic Warm-Start, where an Advisor selects up to three distinct Phase-D candidates from the low-cost regime and each parallel worker starts from one candidate with locally contracted bounds; and dual-granularity sensitivity grounding, where two Automatic Relevance Determination (ARD) Gaussian processes — Global Sensitivity on all evaluated designs and Elite Sensitivity on the top 15% of designs — yield feature importance from ARD lengthscales (S_d ∝ 1/ℓ_d) for the final design report.

4. A benchmark and evaluation protocol of 12 sizing tasks covering six circuit topologies (NMCNR, DFCFC, PFC, Miller Op-Amp, Class-AB Op-Amp, Discrete Op-Amp) and four technology platforms (SKY130, PTM 45 nm, PTM 180 nm, discrete MOSFET), with two specification sets per circuit, five independent runs per task, and a task-level cluster bootstrap for confidence intervals.

Main Findings

• Sizing performance improves over the baseline: VLM-CAD achieves a pooled Strict Pass@1 of 23.3% [10.0, 36.7] and a Relaxed Pass@1 of 91.7% [80.0, 100.0] across the 12 tasks, compared with 3.3% [0.0, 8.3] Strict and 15.0% [0.0, 36.7] Relaxed for the EESizer baseline. Pass@3 rises from 10.0% to 46.7% (Strict) and from 16.7% to 99.2% (Relaxed) with corresponding 95% intervals of [22.5, 71.7] and [97.5, 100.0] for VLM-CAD, versus [0.0, 25.0] and [0.0, 41.7] for EESizer. VLM-CAD matches or exceeds EESizer on every task.

• General-purpose VLMs show spatial blindness on schematics: Evaluated on 122 visually noisy schematics, functional accuracy was 95.90% for Gemini 3 Flash Preview, 49.18% for GPT-5.2, 52.46% for Gemma-4-31B-it, and 58.20% for Qwen3-VL-235B-A22B-Instruct, compared with 68.85% for Image2Net. Connectivity scores were 0.6600 ± 0.1652, 0.6096 ± 0.1278, 0.5918 ± 0.1202, and 0.5751 ± 0.1091 respectively, versus 0.8121 ± 0.2116 for Image2Net. Both GPT-5.2 and Qwen3-VL-235B-A22B-Instruct returned non-empty output for only 119 of the 122 schematics, while Gemini 3 Flash Preview, Gemma-4-31B-it and Image2Net returned output for all 122.

• The parser is not uniformly best: Image2Net attains 68.85% functional accuracy, below Gemini 3 Flash Preview's 95.90%. The authors therefore offload deterministic netlist recognition to Image2Net while the VLM performs high-level circuit reasoning, and note Image2Net remains imperfect under novel noise.

• Ablations reveal a negative-transfer effect: With Gemma-4-31B-it, ablating Image2Net's annotation and JSON (Ablation 1) performed worse and took longer than providing no schematic at all (Ablation 2) on the Miller Op-Amp, with both ablations showing higher and more unstable universal cost than VLM-CAD. On the Class-AB Op-Amp, both ablations met specifications, and the no-schematic ablation could be competitive on easier settings.

• Runtime is dominated by the simulation-driven optimization stage: For the trials selected by lowest universal cost, total runtime was 2,432.52 seconds for the Miller Op-Amp and 389.80 seconds for the Class-AB Op-Amp, with Phase E accounting for 87.19% and 40.81% of those totals respectively.

• Failure signatures differ by circuit: Strict Pass@1 is zero on six of the twelve tasks. Bandwidth limits the Discrete Op-Amp and the Class-AB Op-Amp (UGBW falls just below target while other metrics pass); gain limits DFCFC by a wide margin; negative phase margin dominates NMCNR and PFC. The Miller Op-Amp tasks on 45 nm BSIM PTM are the only ones combining a marginal gain miss with a phase-margin collapse under an aggressive 18 MHz UGBW target, and Miller Op-Amp SpecsB is the sole task whose Relaxed Pass@1 falls to 40%.

• Sensitivity reporting is delivered: The final design report separates stability-critical parameters from performance-tuning parameters using Global and Elite ARD sensitivity, providing simulation-grounded quantified explainability rather than qualitative chain-of-thought claims.

Methodology in Plain English

The workflow mirrors how an expert designer works, but assigns each step to a specialized agent.

First, instead of asking a vision-language model to read a circuit drawing directly, the authors run the schematic through Image2Net. A trained object detector finds component symbols and their terminal positions; classical corner detection plus clustering cleans up the wiring nodes; a graph algorithm traces connections along horizontal, vertical and diagonal lines; and the result is written out both as a color-coded annotated image and as a structured JSON description of which components connect to which. This gives the language model a factual topology to reason over rather than pixels it might misread.

Second, four specialist agents analyze the problem: a Circuit Explainer identifies analog sub-blocks and signal flow, a Matching Finder flags transistor clusters that must be symmetric and emits equality constraints, a DC Goal Setter assigns each transistor target overdrive voltage, drain-source voltage and current density plus a global biasing plan with headroom and start-up conditions, and an Initial Designer fills every required design variable with a conservative executable value.

Third, DC-OP sizing runs before expensive full simulations: a DC Reviewer runs a fast operating-point simulation, compares node voltages and device operating points against the DC goals and counts discrepancies as a stopping criterion, while a DC Sizer updates parameters using analog design heuristics while preserving testbench values, matching constraints and physical bounds.

Fourth, inference-only sizing optimizes all specifications using only the language model's knowledge of analog circuit theory — no external numerical optimizer. A universal cost function J(x) blends measured power against its limit, weighted violations of lower-bound metrics (such as gain and phase margin) and upper-bound metrics (such as THD and offset), and a large sanity penalty for loss of basic functionality. Above the regime boundary (set at J(x) ≤ 1) the sizer drives every specification except power toward target; inside the low-cost regime it shifts to minimizing power under periodic re-verification. A loop terminated when J(x) < 0.5 or every hard specification was met. A Specs Reviewer verifies the DC operating point first and halts early on biasing failure, and a dead-loop detector perturbs transistor widths if a proposal repeats.

Fifth, when inference-only sizing plateaus, ExTuRBO takes over. Because standard trust-region Bayesian optimization starts from Latin Hypercube Sampling across the whole design space, ExTuRBO instead seeds from up to three distinct low-cost Phase-D candidates and contracts bounds locally — for a 48-dimensional problem with a span ratio r = 0.4, the search volume shrinks by roughly a factor of 10^19. After optimization, two ARD Gaussian processes produce the sensitivity evidence in the design report.

Evaluation compared VLM-CAD against EESizer under each method's default configuration, all using Gemma-4-31B-it as the backbone VLM, with five independent runs per task and Pass@k computed from the number of successful runs. Runs counted as Strict when all performance and power constraints were satisfied, and Relaxed when the power constraint was disregarded and at most one other specification was violated. Simulations used Ngspice-46 with DC operating-point, AC and transient analyses on an AMD EPYC 7513 server with 64 cores, 256 GB RAM and four NVIDIA RTX 4090 GPUs, serving Gemma-4-31B-it locally with vLLM at tensor parallelism 4, maximum model length 126,000 and GPU memory utilization 0.96. EESizer ran up to 25 optimization iterations per run; VLM-CAD's DC-OP and inference-only phases ran up to 10 and 40 iterations respectively. ExTuRBO used up to three parallel workers, a 20-point initial cloud, a default local span of 40% around the seed, a 400-simulation budget per worker, and local bounds spanning 0.8 to 3.0 times the seed value. Universal cost penalty weights were 1.0 for gain, 0.1 for phase margin, 0.2 for UGBW, 0.5 for THD and 10.0 for offset, plus a sanity penalty of 100.0.

Why This Matters

• Impact on research: The paper argues that purely neural reasoning over dense engineering diagrams is unreliable, and demonstrates a hybrid pattern — deterministic symbolic parsing to anchor a language model's high-level reasoning, plus a numerical optimizer that returns quantified sensitivity evidence rather than qualitative chain-of-thought claims. It also supplies a structured comparison against prior frameworks (LLMACD, AnaFlow, EESizer), all of which use netlist text only, netlist inference, and qualitative LLM explainability, whereas VLM-CAD adds schematic modality, ARD-based quantified explainability, and collaborative semantic warm-start initialization.

• Real-world applications:

  • Analog and mixed-signal IP design teams needing to size amplifier blocks across multiple process nodes (the benchmark spans SKY130, PTM 45 nm, PTM 180 nm and discrete MOSFET devices).
  • Design-space triage, where a quantified sensitivity report distinguishes parameters that must be tuned for stability from those that mainly affect performance.
  • Automated migration of an existing schematic to a new technology platform or a tightened specification set, such as the two specification sets defined per circuit in this study.
  • Documentation and sign-off support, where every chosen transistor size is accompanied by simulation-grounded sensitivity evidence.

• Industry relevance: The authors frame industrial-grade design as requiring rigorous justification for every transistor size, and describe the lack of quantified sensitivity analysis as keeping automated sizing methods as "experimental curiosities rather than practical tools for production." The paper also notes end-to-end runtime remains dominated by the simulation-driven ExTuRBO stage — 87.19% of total runtime on the Miller Op-Amp — which is the practical bottleneck for deployment.

Future Directions

• Broadening beyond amplifiers: The benchmark concentrates on analog amplifier topologies, so the authors state that generalization to ADCs, PLLs and power-management blocks remains open.
• Reducing parsing error propagation: Image2Net's connectivity score of 0.8121 ± 0.2116 means parsing errors can propagate into Phase B reasoning and later initialization, motivating more robust parsing under novel noise.
• Diagnosing the remaining failure modes: The paper lists narrow feasible regions from coupled gain, bandwidth, stability and power constraints, short-channel effects weakening long-channel sizing heuristics, and warm-started trust regions entering locally attractive but infeasible basins as plausible contributors — and explicitly treats these as hypotheses rather than causal findings, leaving them for follow-up work.
• Understanding the negative-transfer effect: Ablation 1 (schematic only, without Image2Net annotation or JSON) performed worse than providing no schematic at all on the Miller Op-Amp, which the authors link to the dense, repetitive schematic acting as a naturally adversarial visual input; the conditions under which this occurs are not yet characterized.

Target Audience

This paper benefits most readers working at the intersection of AI agents and electronic design automation: analog and mixed-signal circuit designers interested in automated sizing, EDA researchers studying multimodal and agentic design workflows, and machine learning researchers interested in neuro-symbolic grounding of vision-language models for dense engineering documentation. Engineers evaluating whether language-model agents can be trusted for production design decisions will find the sensitivity-evidence mechanism and the honest failure analysis (Strict Pass@1 of zero on six of twelve tasks) the most useful parts. Readers without analog design background can still follow the workflow structure, but the specification tables and per-circuit failure discussion assume familiarity with metrics such as phase margin, UGBW, THD and offset.

Authors’ abstract

Vision Language Models (VLMs) have demonstrated remarkable potential in multimodal reasoning. However, they can have spatial blindness and logical hallucinations when interpreting densely structured engineering content, such as analog circuit schematics. To address these challenges, we propose a Vision Language Model-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing (VLM-CAD) designed to support step-by-step reasoning over multimodal evidence. VLM-CAD bridges the modality gap by integrating a neuro-symbolic structural parsing module, Image2Net, which transforms raw pixels into explicit topological graphs and structured JSON representations to anchor VLM interpretation in deterministic facts. To ensure the reliability required for engineering decisions, we further propose ExTuRBO, an Explainable Trust Region Bayesian Optimization method. ExTuRBO employs agent-generated semantic seeds to warm-start local searches and uses Automatic Relevance Determination to provide sensitivity evidence for the final design report. Experimental results on 12 sizing tasks covering six circuits and four technology platforms show that VLM-CAD achieves a pooled Strict Pass@1 of 23.3% and a Relaxed Pass@1 of 91.7%, while providing sensitivity evidence for final design reports.