Towards Tensor Network Models for Low-Latency Jet Tagging on FPGAs

AI summary

Overview

• Research area: Machine learning for real-time data processing in high-energy physics, specifically tensor-network classifiers deployed on FPGA hardware for the Level-1 trigger.
• Technical level: Advanced. The paper assumes familiarity with tensor networks (MPS, TTN), fixed-point quantization, and FPGA synthesis flows, though the motivation and results are explained clearly enough for a physics or ML reader outside hardware engineering.
• Scope: A systematic study of Matrix Product States and Tree Tensor Networks for jet tagging using low-level jet constituent features, covering data embedding, quantization, and FPGA synthesis of latency and resource usage.

What This Paper Is About

The ATLAS and CMS detectors must reduce the LHC's 40 MHz collision rate in real time, and the first-level (Level-1) trigger must do so within a latency budget of 12.5 μs using FPGA hardware. Deep neural networks perform well at this task but are opaque and expensive to implement. This paper asks whether tensor-network models — Matrix Product States (MPS) and Tree Tensor Networks (TTN) — can match deep-learning performance on jet tagging while being compact, interpretable, and fast enough to fit inside the Level-1 trigger latency budget.

Key Contributions

1. A full pipeline for tensor-network jet tagging, spanning quantum-inspired data embedding, model training, post-training quantization, and FPGA synthesis, applied to both MPS and TTN architectures.
2. A quantum mutual information (QMI) analysis used as a design tool: the authors measure correlations inside a trained model and use the result to choose an embedding that reduces long-range correlations, cutting the bond dimension needed for the same expressive power.
3. A post-training quantization study with the integer part fixed at two bits and the fractional bit width varied, comparing quantized versus floating-point contractions for both architectures across N = 8, 16, and 32 jet constituents.
4. Hardware validation on an AMD-Xilinx XCVU13P FPGA, with the TTN implemented in VHDL via Vivado and the MPS implemented in High-Level Synthesis via Vitis HLS, reporting latency, memory, and resource utilization.

Main Findings

• Competitive accuracy from tensor networks: In full 32-bit floating-point precision, TTN models with maximum bond dimension χ = 10 reach test accuracies of 65.3% (N = 8), 72.5% (N = 16), and 77.1% (N = 32). MPS models with bond dimension D = 10 reach 66.1%, 72.0%, and 74.8% respectively. The authors state these are competitive with permutation-invariant deep learning models in Ref. [34] and close to state-of-the-art transformer and MLP-Mixer models in Refs. [45, 27].
• AUC scores per class: At N = 32, the TTN reports AUC of 92.6% (g), 90.4% (q), 94.3% (W), 93.1% (Z), and 94.7% (t); the MPS reports 90.8%, 88.2%, 93.7%, 91.5%, and 93.5%. A 3-fold cross-validation was performed, and all errors are smaller than or equal to 0.1% for both accuracy and AUC.
• Parameter counts: At N = 32 the MPS has 23,478 parameters and the TTN has 22,340; at N = 16, 12,278 and 10,420; at N = 8, 6,678 and 4,460.
• Quantization tolerance differs by architecture: MPS accuracy degrades noticeably when the fractional bit width falls below FB = 8, whereas TTN performance drops significantly only below FB = 6. The TTN reaches higher accuracy and its performance plateau with fewer fractional bits, indicating stronger tolerance to low-precision arithmetic.
• Quantized versus floating-point contractions: For both architectures, the paper compares contractions with quantized weights only (floating-point operations) against fully quantized operations, with the quantized operations degrading performance slightly for the TTN.
• Sub-microsecond latency: All synthesized models exhibit inference latency of order 100 ns. Individual reported latencies are 236 ns (MPS, N = 8, FB = 14), 432 ns (MPS, N = 16, FB = 14), 708 ns (MPS, N = 32, FB = 14), 92 ns (TTN, N = 8, FB = 14), 124 ns (TTN, N = 16, FB = 14), and 156 ns (TTN, N = 32, FB = 14). Latency values are not reported in the table for the reduced-precision MPS rows.
• Resource fitting: All networks fit within the resource limits of the XCVU13P except the MPS with N = 32 and FB = 14, which uses 129% of available DSPs. Reducing the fractional bit width brings that DSP usage down to 60%, making deployment possible.
• DSP usage differs by synthesis route: The VHDL-based TTN implementation completely avoids DSP usage at reduced precision, while the HLS-based MPS synthesis only reduces DSP deployment. The MPS results depend on the Vitis HLS synthesis report, while the TTN values are derived from the Vivado utilization report and are described as fully deterministic and reproducible.
• Memory footprint and quantization savings: Memory ranges from 71 kB (TTN, N = 8, FB = 14) to 383 kB (MPS, N = 32, FB = 14). Lowering precision reduces this substantially — for example, the TTN at N = 16 goes from 166 kB at FB = 14 to 83 kB at FB = 6, and the MPS at N = 32 from 383 kB to 239 kB.

Methodology in Plain English

The authors use the public hls4ml jet dataset from Zenodo, in which each jet is described by 16 kinematic properties of its particle constituents, and they select the N highest transverse momentum particles with N chosen from {8, 16, 32}.

For each particle they keep three features — transverse momentum (pT), relative particle energy with respect to the total jet energy (E_rel), and distance from the jet center (ΔR) — and map them into a polynomial feature vector up to degree two of dimension d = 7. Each particle becomes one site of a tensor product, so the whole jet is a product of these embedded vectors.

The choice of embedding is driven by a diagnostic: the authors train models with different embeddings and compute the quantum mutual information between pairs of inputs, which reveals how strongly inputs are correlated by the model. An initial arrangement produced a chessboard-like correlation pattern with significant long-range correlations; permuting the features so that the pT of all particles come first and ΔR second reduced those long-range correlations. The final embedding stacks the features of one particle on one site with no mixed terms, reducing the problem size from roughly O(d^(nN)) to O((nd)^N).

Two architectures are trained: an MPS, a chain of N tensors with physical dimension d and bond dimension D = 10 with a class-index tensor in the middle, and a TTN, a binary tree with L = log2 N layers, rank-3 tensors, and maximum bond dimension χ = 10. MPS tensors are initialized with normally distributed random values with standard deviation 10⁻²; TTN tensors use the initialization from Ref. [43]. MPS tensors are brought into canonical form with the canonical center on the class tensor.

Training uses 620,000 samples with an independent test set of 260,000 samples, mini-batch gradient descent with the Adam optimizer, and inputs scaled to the [5, 95]% interquantile range. The MPS uses a cross-entropy loss and is implemented with the tn4ml Python library; the TTN uses a mean squared error loss and is implemented with the qtealeaves Python library. Models are post-training quantized with a two-bit integer part and a varying fractional part, and quantized contractions are emulated in software to reflect realistic hardware arithmetic.

For hardware, the MPS inference is written in High-Level Synthesis with Vitis HLS, and the TTN inference is written in VHDL using Vivado, following a previously described implementation. Both are simulated, validated, and synthesized for the AMD-Xilinx XCVU13P FPGA at a 250 MHz clock. The firmware assumes the input embedding and the final argmax classification decision happen off-chip: each feature is supplied to the FPGA already as a d-dimensional vector, and the output probability vector is processed off-chip.

Why This Matters

This work tests whether a mathematically structured, interpretable model class can substitute for deep neural networks in one of the most latency-constrained computing environments in science, where algorithms must be pipelined and fixed-latency by construction. It also demonstrates a concrete way to use a quantum-information measure (quantum mutual information) as an architectural design signal rather than a purely post-hoc analysis tool.

Real-world applications:

• Particle physics triggers: Real-time event selection in the HL-LHC Level-1 trigger, where the 12.5 μs latency budget and limited FPGA resources rule out most conventional deep learning deployments.
• Low-latency edge inference generally: The compression and quantization recipe (feature-importance-guided architecture plus fixed-point post-training quantization) transfers to any setting where inference must be deterministic, sub-microsecond, and fit a fixed hardware budget.
• Hardware-aware model compression: The demonstration that reducing the fractional bit width from 14 to 8 or 6 bits cuts DSP usage and memory by large factors with only small accuracy loss provides a template for deployment engineers.
• Interpretable ML in safety- and resource-critical systems: Because MPS and TTN representations are factorized and linear in structure, their internal correlations can be inspected, which is harder for conventional deep networks.

Industry relevance centers on FPGA-accelerated inference for real-time systems — particle physics experiments, but also networking, sensor processing, and any domain where fixed-latency hardware pipelines are required. The comparison between a low-level VHDL flow and a higher-level HLS flow is directly relevant to engineering teams deciding how much hardware control they need versus how quickly they need to iterate.

Future Directions

• Better quantization methods: The authors propose investigating more advanced numerical quantization techniques (Ref. [13]) or developing ad hoc post-training quantization methods that exploit the gauge freedom inherent in tensor-network architectures.
• Combining feature importance with quantization: The paper suggests that pairing a quantum-inspired measure of feature importance with quantization could compress these models further toward accurate, efficient, ultra-fast inference.
• Extending the design-space study: The authors note that the MPS (HLS) and TTN (VHDL) implementations span the spectrum of design choices, with one prioritizing full hardware control and the other rapid iteration, leaving open which approach suits future TN-based trigger algorithms.
• Open question on latency reporting at reduced precision: The paper reports hardware latency for the full-precision-width configurations and states that reduced-precision models maintain latency, but the table does not list latency values for the reduced-precision MPS rows, leaving the precise latency-accuracy trade-off at lower precision to be characterized.

Target Audience

This paper is most useful to researchers and engineers working at the intersection of machine learning and real-time hardware: physicists and ML practitioners developing trigger algorithms for the HL-LHC, FPGA and HLS engineers interested in low-latency neural network deployment, and quantum-information or tensor-network researchers looking for applied classification problems where compact factorized models have a practical advantage. Readers primarily interested in offline jet tagging performance or in the physics analysis itself would find the hardware and quantization focus more relevant than the classification results.

Authors’ abstract

We present a systematic study of Tensor Network (TN) models $\unicode{x2013}$ Matrix Product States (MPS) and Tree Tensor Networks (TTN) $\unicode{x2013}$ for real-time jet tagging in high-energy physics, with a focus on low-latency deployment on Field Programmable Gate Arrays (FPGAs). Motivated by the strict requirements of the HL-LHC Level-1 trigger system, we explore TNs as compact and interpretable alternatives to deep neural networks. Using low-level jet constituent features, our models achieve competitive performance compared to state-of-the-art deep learning classifiers. We investigate post-training quantization to enable hardware-efficient implementations without degrading classification performance or latency. The best-performing models are synthesized to estimate FPGA resource usage, latency, and memory occupancy, demonstrating sub-microsecond latency and supporting the feasibility of online deployment in real-time trigger systems. Overall, this study highlights the potential of TN-based models for fast and resource-efficient inference in low-latency environments.