PCBRouteAgent: How Close Are LLM Agents to Becoming PCB Routing Engineers?

AI summary

Overview

Research area: AI agents for electronic design automation (EDA), specifically LLM-driven printed circuit board (PCB) routing; intersects multimodal agent design, planning-and-execution architectures, and hardware design tooling.

Technical level: Advanced. The paper assumes familiarity with PCB routing concepts (nets, vias, design rules, copper layers), KiCad’s push-and-shove router, and LLM agent architectures.

Scope: The paper presents PCBRouteAgent, a two-level multimodal LLM agent that separates board-level routing planning from geometric trace execution on KiCad, and benchmarks it against rule-based routers and PCBWorld LLM/RL agents across 247 boards in four PCBWorld-Bench test splits.

What This Paper Is About

PCB routing—turning a netlist into physical copper traces and vias that obey clearance, width, and layer rules—is still largely manual engineering work, and automated routers need careful tuning on complex boards. Recent work (PCBWorld) gave LLM agents direct access to KiCad’s native routing operations, but those agents still trail rule-based routers, because having tools and feedback does not by itself give an agent a board-level strategy. PCBRouteAgent’s goal is to close that gap by mimicking how a human routing engineer alternates between global strategy (which nets to route first, in which regions, on which layers) and local geometric execution, revising the strategy when the board pushes back.

Key Contributions

1. A two-level multimodal agent architecture for PCB routing. A Global Routing Planner consumes board images plus structured electrical/geometric text to produce routing guides; a Detailed Routing Executor realizes those guides through KiCad’s native push-and-shove (PNS) router. The split mirrors the global/detailed decomposition used in IC routing flows such as OpenROAD, adapted to PCBs.

2. Connectivity planning as a minimum spanning tree (MST) problem over disconnected pad clusters. For each net, clusters are vertices and candidate inter-cluster connections are edges weighted by minimum Euclidean pad distance with a penalty for incompatible pad layers, yielding Kn − 1 connection tasks for Kn clusters. Routing order is initialized by total estimated spanning-tree length (shorter nets first).

3. Spatial and layer guidance that deliberately stops short of exact geometry. Corridors are axis-aligned bounding boxes of connection endpoints expanded by a margin δ = 1.5 mm; when a net must change layers, the connection is split at its midpoint into two layer-specific corridors plus a via-transition region rather than a fixed via location, leaving local search to the executor.

4. Feedback-driven replanning through validated structured “guide patches.” When local recovery fails, the executor emits a structured feedback packet (attempted operations, last reached position, blocking obstacles, deviations from guidance). The planner returns a patch that locally edits endpoints, corridors, via regions, or routing order while preserving already-accepted routes, with a validation-and-correction step before execution resumes.

5. A broad evaluation on 247 boards (128 synthetic from D2-test, 99 D3-A, 10 D3-B, 10 D3-C real-world open-source boards), including a same-model ablation isolating the framework from the underlying LLM.

Main Findings

• Synthetic boards (D2, 128 boards): PCBRouteAgent reaches a 1.00 clean-pass rate and 1.000 routability with both Claude Haiku 5.5 and Claude Opus 5.5, matching Freerouting and KiCadRoutingTools on completion. The Opus variant’s potential gain is 16.27, versus 15.84 for PCBWorld PPO and 14.42 for Freerouting, with 4.2% shorter wirelength and 19.7% fewer vias than Freerouting.

• Small real-world boards (D3-A, 99 boards): Opus achieves 0.949 clean pass and 0.994 routability with an average of 0.09 design-rule violations. The paper’s abstract reports this as 13.9 percentage points above the best evaluated baseline (PCBWorld PPO w/o finish at 0.810), while the introduction instead states 19.9 points over Freerouting (0.750); both comparisons appear in the text. The published PCBWorld GPT-5.4 agent scores 42% here.

• Medium real-world boards (D3-B, 10 boards): Opus reaches 1.000 clean pass versus 0.640 for Freerouting, and 0.00 for the PCBWorld GPT-5.4 agent and for PCBWorld–Haiku. This result includes retries of unscored model-response failures plus angle repair, so the authors explicitly note it is not a strict first-attempt (@1) estimate.

• Large real-world boards (D3-C, 10 boards, >100 pads): Opus reaches 0.40 clean pass versus 0.30 for Freerouting and 0.00 for the evaluated RL baselines and PCBWorld–Haiku, with 0.949 mean routability and average DRV reduced from Freerouting’s 32.0 to 6.3 per board (an 80.3% reduction). Six of the ten boards remain incomplete, exposing the gap between high average routability and whole-board success.

• Framework effect under a fixed backbone: With the same Claude Haiku 5.5 model, PCBRouteAgent achieves clean-pass rates of 1.00, 0.929, 0.80, 0.10 on D2/D3-A/D3-B/D3-C versus 0.633, 0.343, 0.00, 0.00 for PCBWorld–Haiku—improvements of 36.7, 58.6, 80, and 10 percentage points—and raises mean routability from 0.897 to 1.000, 0.721 to 0.990, 0.442 to 0.997, and 0.199 to 0.915.

• Efficiency: Across all 247 boards, the same-model comparison cuts model calls from 22,529 to 172, tokens from 105.7M to 12.0M, API cost from $20.72 to $4.77, and cumulative per-board runtime from 36.4 to 2.6 hours (approximately 131×, 8.8×, 4.3×, and 14× respectively).

• Completion does not equal short routing: On D3-B, the Opus variant uses 10.9% more wirelength than Freerouting while improving clean-pass rate, and on D3-C its wirelength (1410.5 mm) exceeds the Reference design’s 1391.0 mm.

Methodology in Plain English

The agent is built around a division of labor that mirrors a human engineer’s workflow.

Step 1 — See the board two ways. For each board, the system builds a multimodal representation: four images (overall layout, front copper, back copper, and outstanding connectivity demands) plus structured text listing pad coordinates and geometries, layer information, net assignments, connectivity clusters, and design rules. Images give spatial context; the text gives exact identifiers and numbers.

Step 2 — Plan the topology cheaply. Within a net, pads already connected by copper form clusters. Rather than searching all possible ways to link clusters, the planner builds a minimum spanning tree where edge weights are pad-to-pad Euclidean distances with penalties for pad-layer mismatches, giving a compact set of connection tasks. Nets are ordered by estimated total connection length, shortest first.

Step 3 — Give spatial hints, not exact paths. Each connection gets a rectangular corridor (the endpoints’ bounding box plus a 1.5 mm margin). If the endpoints are on different layers, the connection is split at the midpoint into two corridors with a candidate via region in between. This avoids committing to precise trace shapes before obstacles are known.

Step 4 — Execute with a real router and local repair. The executor turns guides into tasks, picks source and target anchors, generates candidate waypoints between adjacent corridors, and calls KiCad’s PNS router. Before escalating a failure, it tries bounded local fixes: walkaround and shove, alternative waypoints, a grid-based A* detour, backtracking to earlier stages, and alternative anchors—capped by fixed retry budgets (two stage backtracks, one A* detour, two alternative-anchor attempts per connection, at most one rip-up per obstructing net).

Step 5 — Replan only when needed. If local recovery is exhausted, failed tasks roll back to a checkpoint while accepted routes are preserved, and a structured feedback packet goes to the planner. The multimodal LLM returns a small patch to the guide, which is validated for consistency and valid references (with a correction pass if it fails), then merged and recompiled for execution. The loop terminates when all target connections are done, no tasks remain, or the budget (per-board replanning budget of 12, at most four replans per connection, five batch-replanning rounds) is exhausted.

Evaluation discipline. Final boards are scored by KiCad, not by the agent’s self-report. A board passes only if every required connection is complete and KiCad reports zero error-level design-rule violations.

Why This Matters

The work shows that the bottleneck for LLM agents on physical design tasks is not tool access or model reasoning in isolation, but architecture—an explicit global-plan/local-execute/feedback split. With the same Claude Haiku 5.5 backbone, swapping the framework moved D3-B from 0% to 80% clean pass, which is a strong argument that agent scaffolding, not just model scale, determines hardware-design competence. It also supplies a non-trivial benchmark result: a 40% clean-pass rate on large boards versus 30% for a mature rule-based router, plus an 80.3% DRV reduction, while using roughly 131× fewer model calls than a per-step agent.

Real-world applications:

• EDA tooling: embedding a planning layer above existing autorouters (the paper’s use of KiCad’s PNS router is a template other vendors could follow).
• Prototyping and small-batch hardware: the D3-A/D3-B results target small and medium open-source boards, the scale typical of hobbyist, startup, and lab projects.
• Design-rule cleanup: even when routing is incomplete, the DRV reduction on large boards points to use as an assisted-cleanup or design-review step.
• Agent research infrastructure: the two-level plan/execute pattern with structured failure feedback generalizes to other tool-mediated physical tasks.

Industry relevance: PCB routing labor is expensive and hard to automate reliably; a framework that reaches 100% clean pass on medium real-world boards and beats Freerouting on all three real-world splits—while cutting API cost to $4.77 for 247 boards—is directly relevant to EDA vendors and hardware teams weighing agentic automation.

Future Directions

• Closing the large-board gap. D3-C remains at 0.40 clean pass with six of ten boards incomplete despite 0.949 routability—so the open problem is finishing the last few hard nets, not connecting most of them. The evaluated D3-B and D3-C subsets are two-layer boards, leaving multilayer and high-density designs untested.

• Better anticipation of congestion during planning. The paper attributes failures to heuristic cost estimates and corridor guidance that cannot foresee geometric constraints; learning or simulating downstream feasibility inside the planner is a natural next step.

• Stronger and cheaper replanning. Guide patches are text-level edits validated by rules. Whether the planner could instead learn from accumulated execution traces (or be trained with RL on top of the feedback loop) is untested here.

• Stricter, apples-to-apples evaluation. The D3-B number includes response-failure retries and up to five guarded angle-repair passes, and PCBWorld publishes no D3-C scores, so all D3-C baselines are local re-runs. Establishing a strict first-attempt protocol, and a published Opus comparison against PCBWorld’s interactive agent (skipped here because per-step invocation was verified to cost substantially more), would sharpen the claims.

Target Audience

Researchers in AI-for-EDA and LLM agent design; PCB and hardware engineers curious about what agentic autorouting can currently deliver; benchmark and evaluation researchers working on tool-grounded agents; and graduate students studying planning–execution architectures for tasks where a domain engine, not the model, decides success. Readers wanting a quick sense of the state of the art should start with Tables 1–4 and the same-model Haiku comparison, which isolates the framework’s contribution from the choice of LLM.

Authors’ abstract

Automating printed circuit board (PCB) routing requires coordinating board-level connectivity decisions with geometric execution under strict design rules. Although recent agents can interact with native routing tools, reliable routing on complex boards remains challenging. We present PCBRouteAgent, a multimodal PCB routing agent inspired by how human engineers coordinate global strategy with local execution. A Global Routing Planner combines board images and structured…