Infinite-Precision Autoregressive Modeling for Vector Graphics and Layouts

AI summary

Overview

• Research area: Generative machine learning — autoregressive sequence modeling for vector graphics and engineering layouts
• Technical level: Advanced (assumes familiarity with autoregressive transformers, diffusion models, and tokenization)
• Scope: Introduces IPAM, an autoregressive framework that jointly generates discrete and continuous values at full precision, plus a new semiconductor layout benchmark (ContLayNet) with functional correctness metrics.

What This Paper Is About

Most autoregressive generative models convert continuous quantities—like coordinates in SVG paths or positions in a circuit layout—into discrete tokens. This quantization imposes a hard ceiling on precision, which is tolerable for images but catastrophic for domains like semiconductor design where nanometer errors cause functional failure. The authors build a framework that predicts discrete values categorically and continuous values via diffusion, so that precision is not bounded by vocabulary size, while still permitting variable-length sequence generation.

Key Contributions

1. IPAM (Infinite-Precision Autoregressive Model): A unified autoregressive architecture that jointly models discrete identifiers and continuous vectors within variable-length sequences, using an "atomic unit" representation [d, c] where d is discrete and c is a continuous vector.
2. Length-control mechanisms: An MLP-based end-of-sequence (EOS) logit adjustment that lets the model audit the full sequence state before terminating, plus a differentiable length regularization loss that aligns generated sequence lengths with targets during training.
3. ContLayNet benchmark: 334,330 real-world semiconductor layout samples at 15-bit effective precision, accompanied by four Design Rule Check (DRC) metrics—PDC, CLC, HSC, VSC—that quantify functional correctness rather than perceptual similarity.
4. Cross-domain validation: Demonstrates gains over discretization-based and fixed-schema baselines in three domains: semiconductor layouts, graphic layouts (PubLayNet, Rico), and text-to-SVG icons (FIGR-8-SVG).

Main Findings

• Discretization has exponential scaling costs: Matching continuous precision requires vocabulary sizes that grow as 2^P, where P is bits of precision. A 200×200 integer grid yields only ~7.6 bits—nowhere near circuit-design requirements.
• IPAM dominates on ContLayNet: In completion tasks (given 50 or 100 layers), IPAM roughly halves the violation rates of LayoutTransformer (LT, 18-bit) and DLT across all DRC metrics. For example, CLC at 50-layer completion drops from 0.397 (LT) and 0.227 (DLT) to 0.088.
• Both length-control components matter: Removing the EOS logit MLP, the length loss, or both degrades every metric. The full model achieves near-zero mean length error (μ = 0.15) versus μ = 38.91 without them.
• Baselines fail to scale precision: IconShop on FIGR-8-SVG works at 8-bit but collapses at 9–10 bits; LT requires 18-bit quantization and produces oversized, overlapping layers. IPAM operates at effectively infinite precision.
• Strong graphic layout results: On PubLayNet and Rico, IPAM achieves FID scores of 4.58 and 9.77 (completion), far below LT (186.61, 24.32) and DLT (35.80, 20.92), with competitive overlap and alignment.
• Practical inference trade-offs: At 50 diffusion steps with Improved DDPM, IPAM runs comparably to LT (~877s vs 766s for 100 samples) while far exceeding its quality; at 20 steps it is faster than LT with quality still superior. DDIM was both slower and lower quality than Improved DDPM.

Methodology in Plain English

Every element in these domains can be viewed as an atomic unit: a discrete label (e.g., "power layer" or "M command") bundled with a set of continuous numbers (e.g., x, y, width, height). IPAM embeds each unit by concatenating a learned embedding of the discrete label with a linear projection of the continuous vector.

A transformer decoder reads all previous units and produces a latent vector z. That latent vector feeds two parallel prediction branches:

• Discrete branch: an MLP + softmax predicts the next label categorically.
• Continuous branch: a small diffusion MLP (following MAR's design with AdaLN residual blocks) denoises the continuous values conditioned on z.

Crucially, because continuous targets are never quantized, precision is limited only by floating-point arithmetic. To stop generating at the right time, the model adds a context-dependent MLP term to the EOS token's logit, and a differentiable expected-length penalty (computed from EOS probabilities at each step) nudges the model toward target lengths. Training combines cross-entropy on labels, denoising score matching on continuous values, and the length loss, with weights λ₁ = 100, λ₂ = 0.1, α = 0.1.

Why This Matters

This work shows that the field's default discretize-everything pipeline is not just inefficient at high precision—it is fundamentally incapable of it. By cleanly separating what should be categorical from what should be continuous, IPAM offers a general template for a wide class of hybrid structured outputs.

Real-world applications:

• Semiconductor layout synthesis and completion: Generating or auto-filling nanometer-scale circuit layouts where design rule violations mean non-functional chips.
• Vector graphics and icon design: Text-to-SVG systems that output smooth, resolution-independent paths without quantization artifacts.
• Document and UI layout generation: Producing publication-quality layouts (papers, slides, mobile interfaces) with precise positions rather than rounded grid coordinates.
• CAD and mechanical/architectural design: Any workflow where geometric tolerances matter and rasterization is unacceptable.

Industry relevance: Semiconductor manufacturing (the paper is partly supported by Samsung Electronics) and design-tool companies stand to benefit directly, but so does any creative or engineering pipeline that currently loses precision through tokenization. The ContLayNet benchmark also gives the community a functional-correctness yardstick where FID-style perceptual metrics are inadequate.

Future Directions

• Long-sequence robustness: The authors acknowledge that error propagation worsens on long layouts; mitigating this is an open problem even for IPAM.
• Inference speed: Diffusion sampling is iterative and slower than non-autoregressive alternatives; better samplers or distillation could close the gap without sacrificing quality.
• Scaling and generalization: Extending the atomic-unit formalism to domains with richer per-unit structure (e.g., hierarchical or nested vectors) and validating on more benchmarks.
• Theory of precision: A more formal treatment of when infinite precision provides measurable functional benefit versus when bounded precision is sufficient would help practitioners decide when to adopt this framework.

Target Audience

ML researchers working on generative modeling, structured output generation, or multimodal tokenization; graphics and vector-graphics practitioners; and semiconductor/EDA engineers interested in learned layout synthesis. The paper is accessible to readers with intermediate background in transformers and diffusion models, but newcomers to those topics will need to consult the cited foundations (Vaswani et al., Li et al.'s MAR, Nichol & Dhariwal's DDPM).

Authors’ abstract

While Transformer-based autoregressive models excel in data generation, their token discretization strategy inherently limits their precision in continuous domains. We analyze the scalability limitations of existing discretization-based approaches for generating hybrid discrete-continuous sequences, particularly in high-precision domains such as logos, layouts, and semiconductor circuit designs, where precision loss potentially leads to visual artifacts, aesthetic degradation, and even functional failure. To address the challenge, we propose a novel unified framework that jointly models discrete and continuous values for variable-length sequences. Our approach employs a hybrid approach that combines categorical prediction for discrete values with diffusion-based modeling for continuous values, incorporating two key technical components: an end-of-sequence (EOS) logit adjustment mechanism that uses an MLP to dynamically adjust EOS token logits based on sequence context, and a length regularization term integrated into the loss function. Additionally, we present ContLayNet, a large-scale benchmark comprising 334K high-precision semiconductor layout samples with specialized evaluation metrics that capture functional correctness, where precision errors significantly impact performance. Experiments on multiple domains show that our approach achieves higher-fidelity hybrid vector representations than discretization-based and fixed-schema baselines, while effectively scaling to high-precision generation.