DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior

AI summary

Overview

Research area: Machine learning for electronic design automation (EDA) — graph neural network representation learning for digital circuit design, specifically Register Transfer Level (RTL) circuits and their runtime behavior.

Technical level: Advanced. The paper assumes familiarity with graph neural networks, heterogeneous graph transformers, and digital hardware concepts such as RTL, netlists, control data flow graphs, registers, wires, and clock cycles.

Scope: The paper introduces DR-GNN, a graph neural network pre-trained on an operator-level Control Data Flow Graph (CDFG) plus circuit simulation traces, which learns a unified representation of how circuits behave dynamically across clock cycles and transfers that representation to power estimation and assertion prediction.

What This Paper Is About

Most existing deep learning models for circuits learn only from static information — hardware source code or netlists — so they capture a circuit's structure and semantics but not how it actually behaves while running under a given input sequence. That dynamic behavior (which branches are taken, how often variables toggle, how much power is consumed) is what verification, power estimation, and optimization tasks depend on. This paper's goal is to train a model that learns circuit representations directly from multi-cycle execution behavior, and to build the first large dataset that makes such training possible.

Key Contributions

1. The first dynamic circuit dataset. The authors assemble over 6,300 diverse Verilog designs together with their CDFGs and 63,000 simulation traces, using branch execution and variable toggle information as training supervision. Designs range from 10 to over 500 CDFG nodes, with an average of 51 nodes per design, and include RISC-V components, SoC components, accelerator modules, and custom IP blocks.

2. DR-GNN, a dynamic-behavior-aware GNN. The model is built on an operator-level CDFG of the RTL design rather than a netlist or statement-level graph, and uses a circuit-specific propagation mechanism — semi-decoupled aggregators for operator groups plus a position-aware operator messaging mechanism in a heterogeneous graph transformer.

3. State-of-the-art pre-training results. The authors report an average accuracy of 94.80% in branch hit prediction and 94.25% in toggle rate prediction, outperforming GCN, GAT, Gated GCN, GATv2, HGVC-based baselines, and Design2Vec.

4. Transfer learning to downstream dynamic tasks. The frozen pre-trained representations reach an average accuracy of 79.60% in power estimation and 87.03% in assertion prediction, including on large-scale designs ranging from 1k to 10k CDFG nodes.

Main Findings

• Pre-training performance: In Table 2, DR-GNN achieves 94.69 ± 0.75 (sequence length 10), 94.75 ± 0.64 (20), 94.98 ± 0.59 (30), and 94.78 ± 0.69 (50) for branch hit prediction, and 93.74 ± 0.41 (10), 93.98 ± 0.47 (20), 94.39 ± 0.34 (30), 94.90 ± 0.36 (50) for toggle rate prediction. The strongest baseline on branch hit prediction is GATv2 at 85.23–86.16 across sequence lengths; Design2Vec reaches 82.03, 86.78, 72.81, and 69.33, and is not evaluated on toggle rate because its nodes represent statements rather than variables.

• Input encoding matters: Ablations comparing binary input encoding against random encoding (dynamic information removed) and decimal encoding show binary vector encoding achieves the best performance.

• Semi-decoupled aggregation wins: Ablations comparing the proposed semi-decoupled aggregators against fully decoupled aggregators (one per operator type) and a single shared aggregator show semi-decoupled aggregation performs best.

• Position-aware messaging wins: Removing operator type or operand position from the attention mechanism degrades results, and the operand position embedding outperforms both global position encoding using Laplacian eigenvectors and relative position encoding using distance embedding.

• Behavior on circuit scale: For designs with fewer than 50 CDFG nodes and 5 layers, DR-GNN exceeds 95% branch hit prediction accuracy and more than 94% toggle rate prediction accuracy; performance is maintained as design size and depth increase.

• Power estimation: Using pre-trained dynamic representations concatenated with node type and width as node features and a frozen DR-GNN plus a GAT, DR-GNN outperforms MasterRTL and HGVC. Using both supervision types beats using only toggle supervision (DR-GNN_ts) or only branch supervision (DR-GNN_bs).

• Large-scale power estimation: On pcie_ctrl (0.9k CDFG nodes, 22k AIG nodes) DeepSeq2 achieves error 0.08 in 14.8 s while DR-GNN achieves 0.15 in 0.17 s; on dma_sched (1.9k / 43k) DeepSeq2 achieves 0.09 in 27.2 s versus DR-GNN 0.14 in 0.29 s. DeepSeq2 runs out of memory (marked MO) on ysyx_cpu (6.0k / 120k), csc_wl_dec (7.4k / 185k), and ch_ctrl (8.3k / 304k), where DR-GNN achieves errors of 0.19, 0.18, and 0.23 in 0.61 s, 0.73 s, and 0.96 s. The conventional EDA flow takes 540 s, 1232 s, 2479 s, 2175 s, and 2896 s on the same five designs.

• Assertion prediction: Across eight assertions, DR-GNN attains 86.98% (v < 4), 87.35% (v < 16), 82.01% (v ≠ 2), 81.36% (v ≠ 4), 91.36% (v1 ≠ v2), 88.72% (v1 < v2), 86.80% (v1 & v2 == 0), and 91.67% (v1 | v2 ≠ 0), with assertion frequencies ranging from 50.89 to 73.98. The full DR-GNN outperforms both DR-GNN_ts and DR-GNN_bs on every assertion.

• Stated limitation: DR-GNN struggles to predict exact values of variables — accuracy is lower on assertions such as v ≠ 2 and v ≠ 4 — which the authors describe as leaving room for improvement.

Methodology in Plain English

The authors convert RTL source code into RTLIL using the Yosys EDA tool, parse that with the Stagira Verilog parser into an abstract syntax tree, and traverse the tree to build an operator-level CDFG. In this graph, nodes are variables (wires and registers), constants, and operators, and directed edges represent data or control flow; register in-edges carry values across clock cycles. Compared with a statement-level CDFG, the operator-level graph reflects the actual data flow inside the circuit and supports multi-bit values.

Each node gets an initial embedding. Input nodes are encoded from the input sequence by embedding each clock cycle's value as a binary vector, using learnable per-bit-position vectors summed and modulated by bit value, then passed through a GRU; this encoder is trained separately via a sequence reconstruction task and then frozen. Constant nodes reuse the same encoding approach. Operator node embeddings start at zero because their values are unknown before simulation.

Propagation follows the heterogeneous graph transformer design but is adapted to CDFG properties. Instead of one aggregator per gate type (impractical for the more than 30 RTL operators) or one shared aggregator, operators are split into five groups — unary (7 operators), binary (20), multary (2), condition (1), and register (1) — where operators in a group share aggregation weights and are distinguished by attention. Attention inputs concatenate the source node embedding, a rotary operand position embedding (needed because operators like subtraction are non-commutative), and the operator type embedding. Messages are aggregated with softmax-normalized attention weights, and node embeddings are updated by a GRU layer; 20 GNN layers are stacked.

Pre-training uses two supervision signals simultaneously: branch hit prediction, where nodes acting as select signals for condition nodes are read out through an MLP, and variable toggle prediction, where variable node embeddings predict toggle rate (toggles divided by total clock cycles). Binary cross-entropy is used for the branch task, mean squared error for the toggle task, and the two are combined. The dataset is split by design into 80% training, 10% validation, and 10% test, so test designs are never seen during training. Models are trained 5 times and mean and standard deviation are reported. For downstream power estimation, a GAT is trained on top of the frozen DR-GNN embeddings; for assertion prediction, an MLP is trained per assertion. Toggle rate accuracy is defined as 1 − |R̂_v − R_v|.

Training and inference run on a single A800 GPU: 60 epochs, Adam optimizer, learning rate 0.0001, batch size 32, about 40 minutes per pre-training epoch and about 0.7 seconds inference per batch; with DR-GNN frozen, power estimation training takes 10 minutes per epoch with about 0.9 seconds inference per batch. Model hyperparameters include input feature size 1536, operation and position embedding sizes of 32, hidden size 1536, 20 GNN layers, 1 GRU layer, a 2-layer task MLP with hidden size 50, and a 5-layer GCN with hidden size 1536 for power estimation.

Why This Matters

Impact on research: The paper argues that circuit representation learning has been limited to static structure and semantics, and that dynamic behavior — which reveals dependencies not visible in static representations — has been largely unaddressed. By releasing a dataset (6,300+ designs, 63,000 traces) and reporting transfer results on two downstream tasks, it establishes dynamic behavior as a trainable representation objective and, per the authors, provides the first unified model that captures the dynamic behavior of hardware designs.

Real-world applications:

• Hardware verification: Branch hit prediction targets coverage metrics used in verification, and assertion prediction checks whether variables satisfy specified conditions under given inputs.
• Dynamic power estimation at early design stages: RTL-level estimation lets designers assess power before committing to a synthesized netlist; DR-GNN outperforms MasterRTL without needing synthesis into a simple operator graph or simulation runs to obtain toggle rates.
• Optimization of large designs: The model handles circuits from 1k to 10k CDFG nodes where a netlist-level approach runs out of memory, and predicts in under a second where a conventional EDA flow takes hundreds to thousands of seconds.
• Early-stage design exploration: The learned representations are described as enabling more accurate power estimation results for circuits at the early design stage.

Industry relevance: The work is conducted with a commercial hardware simulator and a commercial synthesis tool using the NanGate 45nm technology library, in collaboration with industry funding (Huawei Technologies grant No. N2-2c-TH2420350, along with NSFC Grant No. 62090021, the National Key Laboratory for Multimedia Information Processing at Peking University, and Hong Kong RGC grants 14212422, 14202824, and C6003-24Y). The reported runtime gap against a conventional EDA flow (0.17–0.96 s versus 540–2896 s) is directly relevant to EDA tool throughput.

Future Directions

• Exact value prediction. The authors report that DR-GNN struggles with exact variable values, as shown by the lower accuracies on v ≠ 2 (82.01%) and v ≠ 4 (81.36%) relative to other assertions, and explicitly note this leaves room for improvement.

• Additional supervision signals. The paper shows that adding branch supervision to toggle supervision improves both power estimation and every assertion result, and states that supplementing more useful supervisions could help learn a more comprehensive dynamic representation — an open question is which further circuit properties would help.

• Scaling and generalizability. The authors evaluate larger circuits of 1k to 10k CDFG nodes in downstream tasks and show that performance declines as design size and depth grow, raising the question of how far the approach extends beyond the 10–500 node range of the pre-training dataset.

• Broader downstream dynamic tasks. The paper frames power estimation and assertion prediction as demonstrations of transfer, noting that tasks involving hardware verification, dynamic power estimation, and other dynamic-related circuit tasks remain difficult for static models — additional dynamic tasks could test the generality of the representation further.

Target Audience

This paper suits machine learning researchers working on graph representation learning and its application to structured, domain-specific data; EDA and hardware verification researchers interested in learned circuit representations, coverage prediction, and dynamic power estimation; and practitioners at the RTL and architectural design stages who want early-stage prediction without full synthesis and simulation. Readers will need a working knowledge of graph neural networks and digital circuit abstractions to follow the technical details. The dataset, source code, and supplementary materials are available at github.com/magicyang1573/DynamicRTL under a CC BY 4.0 license.

Authors’ abstract

There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these models fail to capture circuit runtime behavior, which is crucial for tasks like circuit verification and optimization. To address this limitation, we introduce DR-GNN (DynamicRTL-GNN), a novel approach that learns RTL circuit representations by incorporating both static structures and multi-cycle execution behaviors. DR-GNN leverages an operator-level Control Data Flow Graph (CDFG) to represent Register Transfer Level (RTL) circuits, enabling the model to capture dynamic dependencies and runtime execution. To train and evaluate DR-GNN, we build the first comprehensive dynamic circuit dataset, comprising over 6,300 Verilog designs and 63,000 simulation traces. Our results demonstrate that DR-GNN outperforms existing models in branch hit prediction and toggle rate prediction. Furthermore, its learned representations transfer effectively to related dynamic circuit tasks, achieving strong performance in power estimation and assertion prediction.