Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

AI summary

Overview

• Research area: Embedded/edge machine learning for brain–computer interfaces (BCIs), specifically hardware-native neural architectures applied to electroencephalogram (EEG) decoding.
• Technical level: Intermediate. The paper assumes familiarity with neural network training, quantization concepts (Binarized Neural Networks), and basic EEG feature extraction, but explains its core mechanism (soft logic gates, thermometer encoding) from first principles.
• One-sentence scope: An iso-parameter benchmark of Differentiable Logic Gate Networks against matched-capacity MLP and BNN baselines on four EEG datasets across two tasks and four parameter tiers, with inference benchmarked on a 7W Nvidia Jetson Orin Nano under single-threaded CPU execution.

What This Paper Is About

Standard deep learning models for EEG decoding rely on floating-point multiply-accumulate arithmetic, which exceeds the power and thermal budgets of portable edge devices and often forces processing to the cloud, adding latency that breaks real-time BCI feedback loops. This paper asks whether Differentiable Logic Gate Networks (Diff-Logic) — networks that train with continuous relaxations of Boolean operations and then "harden" into pure Boolean circuits executable via bitwise CPU operations — can match floating-point accuracy on EEG tasks while delivering lower latency and smaller memory footprints. The authors run controlled, equal-parameter comparisons on binary dementia detection and 3-class emotion recognition to test whether logic-based learning transfers from the tabular and image benchmarks where it was previously demonstrated to noisy, non-stationary brain signals.

Key Contributions

1. First rigorous application of Diff-Logic to EEG decoding. The authors report that Diff-Logic encodes high-dimensional EEG features effectively, matching or outperforming floating-point baselines on emotion recognition and dementia detection across four datasets and four complexity tiers (50k–500k parameters).
2. A soft-to-compiled pipeline from probabilistic training to Boolean inference. The framework trains over a differentiable distribution of 16 possible two-input Boolean functions per neuron, then hardens each gate to a single function and compiles the result into bitwise-executable C, achieving a reported peak speedup of 2.91× over Float32 MLPs on embedded hardware.
3. An iso-parameter evaluation protocol. Diff-Logic, MLP, and BNN models are constrained to approximately equal trainable parameter counts at each tier, so differences reflect representational efficiency rather than capacity; this is paired with edge latency and memory measurements on a power-constrained Jetson Orin Nano.
4. A characterized performance–efficiency trade-off. The study documents flat latency scaling for compiled logic circuits versus linear latency growth for MLP/BNN baselines, plus accuracy behavior including overfitting in Float32 MLPs at higher parameter counts.

Main Findings

• Dementia detection favored Diff-Logic. Diff-Logic reached 80.2% Macro F1 on the CN vs. AD task (100k tier), with scores of 78.9–80.2% across all model scales. The abstract reports this as outperforming the MLP baseline by 6.8%; the results and discussion sections describe a 9.4 percentage-point advantage over the MLP at the 200k tier (80.0% vs. 70.6%), and the conclusion repeats "up to 80.2% Macro F1, outperforming the MLP by 9.4 percentage points."
• CN vs. FTD also favored Diff-Logic. Diff-Logic scored 79.1% at the 100k tier and 76.4% at 200k, versus MLP scores of 75.8% and 70.5% at the same tiers. Chance level for the binary dementia tasks is 50%.
• BNN baselines were unstable on dementia. BNN standard deviations reached ±12 on dementia tasks, which the authors attribute to the gradient approximation methods required for training standard binary networks struggling to converge on high-dimensional EEG data.
• Float32 MLP retained a moderate lead on SEED emotion recognition. On the 3-class task the MLP held roughly 62% versus 55–61% for Diff-Logic, but this gap vanished at the 500k tier (Diff-Logic 61.0% vs. MLP 61.3% on SEED-China). Chance level for the 3-class tasks is 33.3%.
• Diff-Logic latency stayed nearly flat as model scale grew. Inference time remained effectively constant at approximately 0.19–0.22 ms across a 10× increase in model size, while MLP and BNN latency scaled with parameter count.
• Peak speedups on the Jetson Orin Nano. At the 500k tier, Diff-Logic achieved 2.91× speedup over the MLP and 4.33× over the BNN on the dementia task; on SEED the corresponding speedups were 2.30× over the MLP and 0.76× relative to the MLP for the BNN.
• Memory footprint was substantially smaller. At 500k parameters the MLP required nearly 2 MB of storage (1,959 KB) and 0.631 ms per inference, while the equivalent Diff-Logic model used 140 KB and 0.216 ms — a reported 14× reduction in storage. Diff-Logic model size grew only from approximately 52 KB (50k tier) to 140 KB (500k tier).
• Early tiers did not favor Diff-Logic on speed. At the 50k tier Diff-Logic was slower than the MLP (0.193 ms vs. 0.107 ms, a 0.56× speedup factor); the crossover occurred at the 200k tier, labeled "The Efficiency Crossover" in Table 2, where Diff-Logic reached 1.45× on dementia.
• The advantage is attributed to two architectural properties. Structural condensation collapsed a dense search space of 16 operators per neuron into one hard gate per node, reducing active parameter count by a factor of 16×, and bitwise compilation let the model exploit full CPU register width (SWAR) and SIMD instructions.
• Logic sparsity beat weight quantization. Diff-Logic outperformed the BNN despite both using binary operations, because compiled Diff-Logic models are accumulation-free, whereas BNNs require a popcount accumulation step after the XNOR operation.
• Float32 MLPs degraded at larger scales. MLP accuracy on CN vs. AD dropped from 74.8% (50k) to 72.0% (500k), indicating overfitting; the MLP degraded by nearly 8 percentage points on SEED-German tasks at 500k (54.4% to 46.6%). The BNN instead maintained stable SEED-German performance and overtook the MLP on larger-scale SEED-French tasks (57.9% vs. 56.6% at 500k).
• Latency at scale was far below real-time thresholds. At the 500k tier Diff-Logic reached 0.22 ms latency with 140 KB of storage, which the authors describe as nearly two orders of magnitude below the real-time threshold and small enough to fit within the L1/L2 cache hierarchy of most modern microcontrollers.

Methodology in Plain English

The authors selected two EEG problem types to cover clinical and affective domains: a dementia dataset with resting-state recordings from 88 subjects (29 cognitively normal, 36 Alzheimer's disease, 23 frontotemporal dementia) at 500 Hz across 19 channels, and the SEED emotion dataset with its French and German cross-cultural variants (31 subjects total across the three SEED sets) at 200 Hz across 62 channels. In total the framework was evaluated on 119 unique subjects: 88 from the clinical dataset and 31 from SEED.

Features were extracted rather than learned end-to-end. For dementia, Power Spectral Density across five frequency bands produced a 95-dimensional vector (19 × 5) per 10-second non-overlapping window; for SEED, Differential Entropy across five bands produced a 310-dimensional vector (62 × 5) per 4-second window. Features were normalized with fold-wise Min-Max scaling, where the scaling parameters came exclusively from the training partition of each fold to avoid data leakage. Dementia used subject-level 10-fold cross-validation with majority voting over windows, ensuring no subject appeared in both training and test partitions. SEED used trial-level 10-fold cross-validation, which is subject-dependent and mimics an on-device personalization scenario.

Diff-Logic cannot consume continuous values directly, so normalized features were converted to binary via thermometer encoding (unary coding) with T = 15 thresholds. This expanded the dementia input from 95 features to 1,425 binary inputs and the SEED input from 310 to 4,650 binary inputs. Thermometer encoding was chosen over one-hot because it preserves the ordinal magnitude relationships of the signal.

Each Diff-Logic neuron connects two binary inputs, and there are 16 possible Boolean functions over those inputs (AND, OR, XOR, NAND, and so on). During training the neuron holds a softmax distribution over all 16 functions, producing a differentiable probabilistic output that allows gradient descent. As training proceeds the distribution sharpens, and at convergence the highest-probability function is permanently assigned to the neuron, yielding a static Boolean circuit that uses only bitwise operators. Class scores come from a Group Sum operator that partitions final-layer bits into C groups and sums active bits per class, passed through a temperature-scaled Softmax with τ = 30.

Two baselines were compared at matched parameter counts: an MLP with 2–3 fully connected hidden layers, ReLU activations, and dropout of 0.3, and a BNN following Courbariaux et al. with binarized linear layers, batch normalization, sign activations, and a straight-through estimator that clips gradients to zero when |w| > 1. MLP and BNN models received the continuous normalized features directly, while Diff-Logic received thermometer-encoded binary inputs. The SEED dataset started at approximately 74k parameters rather than 50k because LogicLayers require at least ⌈n_in/2⌉ outputs per layer, establishing a hard lower bound.

Training used PyTorch on an Nvidia RTX A6000 with the Adam optimizer for 100 epochs at batch size 128, inverse-frequency class weights for class imbalance, and five independent random seeds per experiment, reporting mean ± standard deviation with Macro F1-score as the primary metric. Diff-Logic used a learning rate of 0.01 following Petersen et al., while MLP and BNN baselines used 0.001.

For edge benchmarking, all models were instantiated on an Nvidia Jetson Orin Nano (8 GB RAM, ARM Cortex-A78AE CPU, Ampere-architecture GPU, 7W TDP) with PyTorch/OpenMP/MKL thread counts set to one. Latency was measured over 10,000 timed iterations after a 5,000-iteration warm-up at batch size 8. Because Diff-Logic inference latency depends only on gate count and connectivity, not on which Boolean functions were assigned, untrained instances produce latency identical to trained networks, avoiding the need to compile all 50 trained checkpoints per tier. MLP and BNN baselines were benchmarked with ONNX Runtime using the single-threaded CPUExecutionProvider.

Why This Matters

Impact on research. This is the first systematic evaluation of true logic gate networks — as distinct from quantized networks — on neurophysiological signals. It shifts the argument about efficient EEG decoding away from "how few bits can we use per weight" toward "can we eliminate accumulation entirely," and it provides evidence that the inductive bias of threshold-based Boolean rules may suit clinical EEG biomarkers that themselves take the form of band-power cutoffs.

Real-world applications:

• Portable, battery-powered dementia screening tools that run entirely on-device without cloud offloading, preserving privacy for sensitive neural data.
• Always-on neural monitoring for seizure detection and other real-time clinical tasks that require microsecond-scale latency budgets.
• Wearable BCI control loops, where CPU-bound logic inference reserves the GPU for concurrent downstream workloads.
• Personalized emotion-recognition interfaces that use a brief on-device calibration phase, matching the subject-dependent protocol the authors used for SEED.

Industry relevance. The 140 KB, 0.22 ms operating point is relevant to embedded silicon and wearable neurotechnology vendors, since it fits within the L1/L2 cache hierarchy of common microcontrollers and removes costly off-chip memory access. The paper positions logic-based networks against the trend toward increasingly parametric EEG foundation models (LaBraM, BIOT, DeeperBrain, and Mamba-based lightweight models such as LUNA and FEMBA), all of which remain dependent on high-precision floating-point arithmetic even after distillation or pruning.

Future Directions

• Extending to raw signals. The current evaluation relies on pre-extracted tabular features, and the standard Diff-Logic architecture does not inherently support temporal or spatial convolutions. Recent convolutional and recurrent extensions of the framework offer a path to end-to-end learning from raw EEG while preserving accumulation-free inference — though thermometer encoding expanded input dimensionality by 15×, which may become expensive at raw-signal dimensionality.
• Interpretability of compiled circuits. The authors can currently observe gate-type distributions and node-selection frequencies per layer, but systematic methods to extract and clinically validate meaningful Boolean decision rules from compiled circuits remain an open challenge and a prerequisite for clinical viability.
• True hardware implementation. Mapping compiled Boolean circuits directly onto FPGA or ASIC primitives without software emulation could bring Diff-Logic substantially closer to ultra-low-power real-time BCI deployment.
• Resolving the accuracy gap on affective tasks. Why Diff-Logic needs higher capacity to match Float32 performance on SEED emotion recognition, while outperforming it on dementia, is not resolved by the reported experiments.

Target Audience

Researchers and engineers working at the intersection of embedded machine learning, brain–computer interfaces, and energy-efficient inference — particularly those designing wearable or implantable neurotechnology where power, memory, and latency are the binding constraints. It is also relevant to practitioners of quantized and hardware-native neural networks interested in alternatives to BNNs, and to clinical EEG researchers evaluating whether logic-based models can express the threshold-style decision rules used in biomarker analysis. Readers need working familiarity with neural network training and evaluation to interpret the iso-parameter comparisons, but no specialized logic-circuit background.

Code is available at: https://github.com/Shyamal-Dharia/eeg-difflogic. The work was supported by NSERC Discovery Grants (RGPIN-2023-03443 and RGPIN-2024-05575) and the Manitoba Medical Service Foundation (grant number 2026-04).

Authors’ abstract

Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic