BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks

AI summary

Overview

• Research area: Machine learning systems and hardware-aware neural network design, specifically gradient-trained lookup-table (LUT) and Boolean-logic neural networks that deploy across GPU, FPGA, and ASIC backends.
• Technical level: Advanced. The paper assumes familiarity with FPGA/ASIC synthesis flows, Boolean truth tables, and differentiable relaxations of discrete functions.
• Scope (one sentence): The paper factors nine published gradient-based LUT-native methods into a single five-axis design space, retrains six of them under one shared protocol, identifies a new best-of-space configuration, and deploys one checkpoint to GPU, FPGA, and ASIC from one code path.

What This Paper Is About

A family of neural network methods replaces multiply-accumulate arithmetic with Boolean lookups, so one trained checkpoint can run as bitwise operations on a bit-packed GPU, map onto FPGA LUT primitives, and synthesize to standard-cell ASIC gates. However, each of the nine known methods (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) ships its own training pipeline, encoder, connectivity rule, fan-in, and hardware-reporting convention, making published numbers incomparable. The goal of BitLogic is to unify these methods into one framework so that the question "which design choices actually matter for accuracy versus hardware cost" can be answered empirically.

Key Contributions

1. The BitLogic framework: A released framework in which five design axes (input encoder, per-layer connection map, per-node Boolean fan-in, node parameterization, and output head) are independently swappable, letting later work evaluate a new axis against the whole published slate with one command. Every prior method becomes one point in this space.
2. A protocol-matched cross-method comparison: Per-axis sweeps on MNIST identify a new best-of-space configuration that no prior paper has trained, and six gradient-trained priors (DiffLogic, PolyLUT, NeuraLUT, DWN, WARP-LUT, LILogicNet) are retrained inside the framework on MNIST, Fashion-MNIST, CIFAR-10, and CIFAR-100.
3. A unified three-backend evaluation: One checkpoint is deployed from a single code path to a bit-packed GPU forward path, Vivado post-route on two Xilinx FPGA targets (Alveo U55C and Zynq UltraScale+ XCZU7EV), and a Yosys plus Nangate 45 nm target-independent ASIC proxy, with Python and deployed hardware accuracy bit-exact by construction.

Main Findings

• Fan-in is the dominant hardware knob. Accuracy grows roughly logarithmically with fan-in n, and the n=2 → 4 step is the largest single lever. At w=32K, n=6 reaches 97.61 ± 0.00% versus 97.12 ± 0.03% for n=4 and 93.75 ± 0.06% for n=2, but the standard-cell cost of n=6 (248,588 ± 779 NAND2-GE at 8K) is about 4 times that of n=4 (60,673 ± 125). On LUT fabrics, n ≤ 6 maps into a single 6-input LUT, so the ASIC knee is real while the LUT-fabric knee is nearly absent.
• Most of DiffLogic's deficit is a fan-in effect, not a parameterization effect. DiffLogic is locked to n=2 by construction and trails the n=4 cluster by roughly 3.6 percentage points in the node-parameterization sweep; under matched n=2, that gap narrows to roughly 2 percentage points.
• The top node-parameterization cluster converges. LightLUT, WarpLUT, and DwnLUT lie within roughly 0.7 percentage points at w ≤ 16K and tighten to roughly 0.3 percentage points at w=32K (96.88–97.11%), suggesting the relaxation family matters less than the literature suggests. LightLUT (soft) is the per-width accuracy winner at 91.14 ± 0.02%, 94.82 ± 0.02%, and 97.11 ± 0.05% at 8K, 16K, and 32K.
• Full-layer learnable connectivity mode-collapses. With no candidate-pool bottleneck, the softmax router drops to 79.10 ± 0.88% at w=1K and 81.47 ± 0.18% at w=4K, 7 to 8 percentage points below every bounded-candidate variant. The apparently low NAND2-GE on that row is a hardware shadow of the collapse, not an efficiency gain. Bounded candidate pools (k=8–16) maximize accuracy, and fixed (random-unique) routing trails the best learnable variant by only about 0.9 percentage points.
• The quantile thermometer's MNIST lead is largely an artifact. At matched nominal bit widths the distributive (quantile) thermometer matches or beats the linear one by roughly 0.5 percentage points, but most of that gain and essentially all the NAND2-GE reduction at b=4 trace to an MNIST-specific threshold collapse, since (pixel > 0) already carries most of the MNIST signal.
• The DSP-backed head is a trade-off, not a free win. The quantized grouped-DSP head buys +0.7 to +4.6 percentage points across the width ladder at 39 DSPs, roughly 10% more FPGA LUTs, and roughly 28% more NAND2-GE; the popcount head is competitive at w=32K (−0.7 percentage points) with zero DSP.
• Best-of-space wins under the shared protocol. The BitLogic best-of-space model wins 62 of the 72 cells (4 datasets × 3 widths × 6 priors); the remaining 10 are DWN out-of-memory entries and are not part of that count. At w=64K it reaches 97.84% (MNIST), 89.16% (F-MNIST), 58.06% (CIFAR-10), and 18.82% (CIFAR-100); the two largest margins are roughly 1.6 percentage points over PolyLUT on MNIST and roughly 5 percentage points over PolyLUT on CIFAR-10.
• Published-versus-retrained gaps trace to disabled machinery. Where published numbers exceed retrained ones by more than about 1 percentage point (DWN on MNIST: 97.80–98.77% versus 87.11%; LILogicNet on MNIST: 97.96–98.95% versus 95.73% at w=64K; NeuraLUT-Assemble at 98.6%), the gap is attributable to method-specific calibration, pruning, or thresholding pipelines that the shared protocol disables on purpose.
• Hardware headline. Deploying the MNIST winner at w=4,000 (88.79% test accuracy, single-seed, within the two-seed 88.94 ± 0.14% band), the pipelined implementation reaches 126.6 MSamp/s on the U55C and 127.2 MSamp/s on the XCZU7EV, roughly 15 times the RTX 3090 and 17 to 18 times the Turing cards, at 6 to 27 nJ per sample, four to five orders of magnitude below GPU. The GPU path itself processes 64 samples per 64-bit operation.

Methodology in Plain English

The researchers first define a common skeleton for any feedforward LUT network: an encoder turns real inputs into binary wires, a stack of Boolean logic layers processes them, and a head turns the final binary vector into class scores. Every published method is then described as a particular choice on five independent axes — encoder, connectivity (which wires feed each node), fan-in (how many inputs each node sees), node parameterization (how the discrete Boolean function is relaxed into something trainable), and head.

They implement all five axes as swappable modules and sweep one axis at a time on MNIST at three widths, holding the other axes at a common base configuration. Combining the per-axis winners yields a new configuration no prior paper had trained. They then retrain six gradient-trained prior methods inside the same framework using one shared recipe (AdamW, constant learning rate 0.01, batch size 128, weight decay 0, no label smoothing or gradient clipping, 100 epochs, two seeds per cell, mean ± std reported) so that the only differences left are each method's design-space coordinates. MNIST and Fashion-MNIST are unaugmented; CIFAR splits use random horizontal flip and random crop. Accuracy is measured on a bit-packed GPU inference path that is bit-exact with the emitted SystemVerilog, so every reported accuracy is simultaneously a deployment accuracy. Finally, the winning checkpoint is emitted to SystemVerilog, placed and routed by Vivado on two FPGA targets, and synthesized through Yosys against Nangate 45 nm as an ASIC proxy.

Why This Matters

• Impact on research: Published LUT-native results have not been directly comparable because each method uses its own pipeline and hardware-reporting convention. BitLogic supplies a shared protocol and a reusable design-space map, letting future work measure a new idea against the entire prior slate rather than against one baseline.
• Real-world applications:
  • Ultra-low-power edge inference where a single checkpoint runs on FPGA without retraining.
  • Always-on sensing and embedded classification, given the 6 to 27 nJ per sample energy figures reported across FPGA modes and targets.
  • ASIC deployment of small feedforward classifiers via a Yosys and Nangate 45 nm flow as a target-independent proxy.
  • Energy-constrained inference generally, in light of the reported context that machine-learning workloads accounted for 10 to 15% of Google's total energy use between 2019 and 2021, roughly 60% of which was inference, and Meta's reported 10:20:70 split across experimentation, training, and inference.
• Industry relevance: The framework targets the practical question of whether a design choice buys accuracy or costs hardware. Findings such as fan-in being the dominant cost lever, full-layer learnable routing collapsing, and node parameterizations converging on fabric backends give concrete guidance, and the FPGA-versus-GPU throughput and energy comparison speaks directly to deployment decisions for small models.

Future Directions

• Depth as the open sixth axis. Every configuration evaluated is two layers deep, and depth was deliberately not swept. Pilot runs reportedly show the soft-versus-hard training gap widening and gradients vanishing through stacked saturating relaxations, so a principled depth axis remains unresolved.
• Architectural extensions beyond feedforward two-layer image classification. Convolutional, residual, attention, and recurrent extensions are explicitly out of scope.
• Reintroducing method-specific machinery in a controlled way. Calibration, pruning, and thresholding were disabled on purpose; quantifying how much of each published number they account for, method by method, is a natural follow-up.
• Resolving the connectivity pathology and scaling to wider cells. The full-layer learnable routing mode collapse has no proposed fix, and the deployed MNIST winner was limited to w=4,000 by the build host, with wider cells left to linear extrapolation at unchanged timing.

Target Audience

Researchers and practitioners working on hardware-efficient neural networks, FPGA or ASIC accelerator design, and quantization or Boolean-logic alternatives to multiply-accumulate arithmetic. It is most useful to readers who already understand LUT primitives, synthesis flows, and gradient-based training of discrete functions, and to engineers deciding which design choices to prioritize when accuracy, throughput, and energy all matter.

Authors’ abstract

Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups. The same trained checkpoint deploys to GPU as bitwise ops on bit-packed activations, to FPGA as LUT primitives, and to ASIC as standard-cell gates, all from one code path. Yet each method ships its own training pipeline, encoder, connectivity rule, fan-in, and hardware-reporting convention. The natural practitioner question, which of these choices actually matter for accuracy and which for hardware cost, therefore has no answer in the current literature. We release \textbf{BitLogic}, a unified framework that factors the field into a five-axis design space (encoder, connectivity, fan-in, node parameterization, head) and instantiates every prior method under one shared training and evaluation protocol. The framework deliberately omits method-specific procedures such as calibration, pruning, and thresholding, and all evaluations are limited to two-layer feed-forward networks. Combining the per-axis winners identifies a new best-of-space configuration that outperforms every retrained prior on every (dataset, width) cell in which every compared prior fits the shared budget, across MNIST, Fashion-MNIST, CIFAR-10, and CIFAR-100. We evaluate the best-of-space model on all three backends. On MNIST, the resulting two-layer network reaches ${\sim}126$\,MSamples/s on FPGA, ${\sim}15\times$ the throughput of a bit-packed GPU forward path that itself processes $64$ samples per $64$-bit operation, at four-to-five orders of magnitude less energy.