AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design

AI summary

Overview

Research area: AI for electronic design automation (EDA), specifically LLM-based agents applied to analog and mixed-signal (AMS) integrated circuit input/output (I/O) subsystem design.

Technical level: Advanced. The paper assumes familiarity with IC design flows, DRC/LVS signoff, tape-out, and LLM agent architectures.

Scope: The paper introduces an LLM-based agent (AMS-IO-Agent) and an accompanying benchmark (AMS-IO-Bench) for automatically generating wirebond-packaged AMS I/O rings from informal pin-planning specifications, validated down to a 28 nm CMOS tape-out.

What This Paper Is About

AMS I/O design is largely manual: engineers must interpret informal pin lists, resolve power-domain and ESD constraints, and hand-assemble layouts that pass design rule checks (DRC) and layout-versus-schematic (LVS) verification. The paper's goal is to build an LLM-based agent that converts ambiguous natural-language design intent into structured, machine-readable representations and then into production-ready EDA scripts, plus a benchmark to measure whether such an agent actually works.

Key Contributions

1. An automatic pipeline for AMS IC I/O generation that formalizes the task into structured steps: intent interpretation, constraint resolution, and generation of EDA scripts.
2. An agent architecture combining a domain-specific knowledge base with structured intent reasoning, supporting generalization across diverse AMS I/O design contexts. The knowledge base is built from training materials of a professional AMS IC design team of more than 10 engineers, validated through over 50 successful tape-out cases, and organized as a lightweight repository of approximately 6k tokens.
3. AMS-IO-Bench, described as the first benchmark suite dedicated to I/O ring generation for wirebond-packaged AMS IC chips, containing 30 cases derived from the I/O planning of 10 real tape-out projects collected over the past 5 years, split into three difficulty levels of 10 cases each.
4. Real silicon validation: an agent-generated I/O ring was fabricated and validated in a 28 nm CMOS tape-out, reported as the first reported human-agent collaborative AMS IC design in which an LLM-based agent completes a nontrivial subtask with outputs directly used in silicon.

Main Findings

• Signoff-level pass rates: AMS-IO-Agent achieves 100% intent graph pass rate and 100% shape validity across backbone models, with up to 76.7% DRC+LVS pass rate (23 out of 30 cases) — the best result, achieved by both Claude-3.7 and DeepSeek-V3, which also each reached 93.33% DRC and 76.67% LVS.
• Model comparison: With GPT-4o as backbone, the agent reached 100% intent graph, 100% shape, 76.67% DRC, 66.67% LVS, and 63.33% DRC+LVS.
• Baseline failure: A baseline LLM (GPT-4o) directly generating code scored 0% on intent graph, shape, DRC, LVS and DRC+LVS, while taking only 0.2 minutes and 1k tokens — i.e., it produced nothing valid.
• Turnaround time: Manual design typically requires around 480 minutes per task (estimated from interviews with 16 PhD-level designers); the agent reduces this to 4.1 minutes (GPT-4o), 4.2 minutes (Claude-3.7), and 5.1 minutes (DeepSeek-V3), with token usage below 200k (160k, 96k, and 105k respectively).
• Ablation with DeepSeek-V3: Removing the knowledge base, intent graph, or adaptor eliminates signoff correctness. Knowledge base alone yields 100% intent graph but only 20.00% shape, 0% DRC, 0% LVS, 27.4 minutes and 2036k tokens. Intent graph without the adaptor yields 100% intent graph, 0% shape, 0% DRC, 0% LVS, with a reduced 2.3-minute runtime because LVS/DRC tools cannot be invoked (18k tokens). Only the full configuration reaches 100% intent graph, 100% shape, 93.33% DRC, 76.67% LVS, 5.1 minutes, 105k tokens.
• Difficulty scaling: All three models passed all 10 simple cases. On medium cases: GPT-4o 7/10, Claude-3.7 9/10, DeepSeek-V3 10/10. On hard cases: GPT-4o 2/10, Claude-3.7 4/10, DeepSeek-V3 3/10.
• Tape-out case study: A 28 nm CMOS prototype, a 1 mm × 1 mm wirebond-packaged mixed-signal IC with 48 I/O pads (12 per side) and multiple power and signal domains, had its inner AMS core implemented by two human designers while the surrounding I/O ring was generated by the agent. A major late pin-order change that would normally require extensive manual redrawing was regenerated and verified within minutes. The combined design passed LVS and DRC, was fabricated, and silicon measurements confirmed correct functionality.
• Benchmark context: Prior complex IC design datasets are small — 17 examples for netlist generation (Ho and Ren 2024) and 24 (Chen et al. 2025) — compared with 30 cases in AMS-IO-Bench.
• Error handling economics: Because tape-out costs greater than $10k per mm² and takes about three months, human engineers act mainly as reviewers; infeasible cases found during execution or via DRC/LVS can be fixed within minutes through prompt refinement or minor EDA edits.

Methodology in Plain English

The agent works in three stages. First, it reads an informal pin-planning specification — a table, spread sheet, or natural-language description — and converts it into an intent graph: a JSON representation of the I/O ring as a sequence of nodes, each a pad or corner cell with attributes such as name, device type, position, direction, and pin connections. The agent fills in what designers conventionally imply (for example, abbreviations like DCLK, VCM, and VREFN suggest signal type, device type, and default direction) and infers elements nobody mentioned, such as corner cells inserted by standard convention.

Second, an intent graph adaptor acts as middleware. Rather than asking the LLM to write Cadence SKILL scripts directly — which the paper says fails for lack of training data — the adaptor uses reusable Python tools for parsing, constraint resolution, geometric calculations, and script generation. It then emits SKILL scripts for schematics and layouts in Cadence Virtuoso and csh scripts to invoke Siemens Calibre verification.

Third, a domain-specific knowledge base of roughly 6k tokens supplies design rules, device specifications, and layout conventions. Its small size means the LLM can consume it directly without retrieval or fine-tuning. Evaluation uses five metrics: intent graph pass rate, shape score (binary pass/fail judged by a vision-language model against a reference), DRC pass rate, LVS pass rate, and the combined DRC+LVS pass rate. The agent was implemented with the Python-based automation framework smolagents, running on a workstation communicating with chip-design server workstations via SSH and socket connections.

The benchmark's three levels are: Simple (10 cases, simplified, small size, single domain), Medium (10 cases, default realism, standard size, multiple domains — each corresponding to a standard MPW chip outline of approximately 1 mm × 1 mm with a single-row I/O ring partitioned into digital and analog power domains), and Hard (10 cases, complex, large size, staggered pads, customized cells — including dual-row or partially dual-row I/O rings, outlines 1.5× to 2× the default size or larger, custom I/O cells such as analog I/O cells with reduced ESD capacitance, and localized ESD power delivery).

Why This Matters

Impact on research: The paper is positioned as the first work to propose both an LLM-based agent and a comprehensive evaluation benchmark specifically targeting real-world AMS IC I/O ring design automation, and the first to carry an agent's output through to fabricated silicon. It also contributes a reusable formulation — structured intent representation plus middleware — for constraint-heavy, project-specific EDA problems where direct code generation fails.

Real-world applications:

• Faster prototype and MPW tape-outs, where I/O ring assembly is a repetitive but error-prone late-stage task.
• Late-stage pin-order and pinout changes, which the case study shows can be regenerated and re-verified in minutes instead of requiring manual redrawing.
• Training and onboarding of entry-level engineers, since the same knowledge base is described as material that engineers with an undergraduate background can master within one to three days.
• Porting to other technology nodes or packaging styles by substituting the knowledge base and execution adaptor, as the authors suggest the methodology applies to AMS layout tasks with regular structures and semantically meaningful signal naming.

Industry relevance: The results target commercially used tools and flows (Cadence Virtuoso, Siemens Calibre) and report token usage below 200k, which the authors argue makes the approach practical for industrial deployment. The stated division of labor — human engineers as reviewers, agent as generator — plus the editable intermediate deliverables (intent graphs and scripts) rather than fixed geometry, matches how design teams actually iterate close to tape-out.

Future Directions

• Extending the approach beyond wirebond-packaged I/O rings to other packaging types such as flip-chip, and to other foundry rules, which the authors identify as a limitation requiring a substituted knowledge base and adaptor.
• Applying the methodology to more complex AMS design tasks beyond I/O rings, as stated in the conclusion.
• Deeper integration with downstream verification and routing tools.
• Determining how much expert review remains necessary for highly customized or unconventional designs, given the authors' explicit statement that the agent cannot fully replace expert review.
• Understanding workforce implications, since the authors note the method may shift demand for certain engineering skills.

Target Audience

Researchers and practitioners at the intersection of LLMs, agents, and EDA; AMS IC design engineers and CAD/automation teams interested in I/O ring and padring automation; benchmark developers working on domain-specific, low-data evaluation for hardware design; and engineering managers evaluating whether agent-generated artifacts are mature enough for tape-out workflows. Readers without a background in IC design or signoff verification will find the contributions conceptually accessible but the significance of DRC/LVS pass rates harder to calibrate.

Authors’ abstract

In this paper, we propose AMS-IO-Agent, a domain-specialized LLM-based agent for structure-aware input/output (I/O) subsystem generation in analog and mixed-signal (AMS) integrated circuits (ICs). The central contribution of this work is a framework that connects natural language design intent with industrial-level AMS IC design deliverables. AMS-IO-Agent integrates two key capabilities: (1) a structured domain knowledge base that captures reusable constraints and design conventions; (2) design intent structuring, which converts ambiguous user intent into verifiable logic steps using JSON and Python as intermediate formats. We further introduce AMS-IO-Bench, a benchmark for wirebond-packaged AMS I/O ring automation. On this benchmark, AMS-IO-Agent achieves over 70\% DRC+LVS pass rate and reduces design turnaround time from hours to minutes, outperforming the baseline LLM. Furthermore, an agent-generated I/O ring was fabricated and validated in a 28 nm CMOS tape-out, demonstrating the practical effectiveness of the approach in real AMS IC design flows. To our knowledge, this is the first reported human-agent collaborative AMS IC design in which an LLM-based agent completes a nontrivial subtask with outputs directly used in silicon.