The Pulse
Micro-Nano Core Raises More Than 1 Billion Yuan in C2 Round
Micro-Nano Core says its C2 round raised more than 1 billion yuan, with JianTou Investment leading and three chips already taped out. The company expects to start customer testing in early 2027, while volume supply depends on customer valid
AI.info Team · Written with AI · fact-checked ·
“全球AI算力正从“训练时代”迈向“推理时代”，端侧与云侧推理需求双爆发，产业正处在智能算力大规模渗透的临界点。”
JianTou Investment, the lead investor
Micro-Nano Core says it has raised more than 1 billion yuan (about $140 million) in a C2 funding round led by JianTou Investment. The company’s October 28 company-news announcement names Hangzhou Capital, Kaitai Capital, Xiaochi Capital, Yantai Caijin, Shengkun Investment, SDIC Taikang and Lingyang Fund among the other investors, alongside existing shareholders who added to their stakes. The round is denominated in yuan, not U.S. dollars. Micro-Nano Core did not disclose a valuation.
Three chips have cleared tape-out
The Hangzhou company says it raised more than 2 billion yuan over the two months covering its C1 and C2 rounds, and 3 billion yuan over six months. It plans to put the money toward chip development and tape-outs, customer testing, computing cards and servers, software tools, supply-chain preparation and customer trials across cloud and edge markets. The fundraising gives the company room to advance products, but its first three chips have not yet reached customer testing.
Micro-Nano Core says three chips across its LP-CIM and PCIe-CIM lines have completed tape-out. The LP-CIM products target low-power inference at the device edge, including AI phones; PCIe-CIM is aimed at higher-performance inference in edge and cloud settings. The company expects to begin formal customer testing in early 2027 and says volume supply will follow customer validation and product certification.
SRAM, DRAM and RISC-V form the pitch
The company’s 3D-CIM architecture combines SRAM compute-in-memory, DRAM near-memory design and a heterogeneous system built around RISC-V. In its account, SRAM-based computation keeps some matrix and vector operations close to stored data, while the DRAM approach seeks to improve memory-compute connections. RISC-V extensions, compilers and software tools are intended to help customers run models on the chips.
Micro-Nano Core says tests of chips from earlier tape-outs showed roughly four to six times the compute density and five to ten times the computational energy efficiency of a conventional von Neumann architecture under matched process, area and precision conditions. Those are company-reported results, not independent comparisons in the announcement; it does not provide the workloads, test setup or outside verification needed to assess them. The company argues that reducing data movement could help inference workloads, where frequent access to model weights and a key-value cache can put pressure on memory bandwidth.
Customer validation is the next test
Micro-Nano Core says it is already working with phone platforms, original design manufacturers and robotics companies on technical alignment, algorithms and product plans. Some edge projects have entered joint debugging, while cloud-service and AI-infrastructure partners are evaluating proposals through proof-of-concept tests. The company does not name those prospective customers or disclose purchase orders.
JianTou Investment’s statement in the company’s financing announcement frames the bet on a shift from training to inference. The company’s own timeline gives that thesis a practical measure: three taped-out chips are due to enter customer testing in early 2027, with batch supply contingent on validation and certification. Until those steps occur, the disclosed progress is funding, tape-out and partner evaluations—not customer-qualified products in volume delivery.