The Pulse
CUDA 13.5 Brings Vera Rubin to General Availability
NVIDIA CUDA Toolkit 13.5 brings general-availability support for Vera Rubin, ready for enterprise production. The release adds GPU scheduling controls, CUDA Tile features and updates to CUDA Python and CCCL.
AI.info Team · Written with AI · fact-checked ·
NVIDIA says CUDA Toolkit 13.5 brings general-availability support for the Vera Rubin GPU architecture, moving it from early developer access to enterprise production. The release also extends Windows on Arm support to NVIDIA DGX Station for Windows. CUDA 13.5 adds new controls for GPU scheduling, alongside changes to libraries, compilers, CUDA Tile and developer tools.
Vera Rubin support reaches GA
CUDA 13.5 supports the Windows Driver Display Model (WDDM) and Microsoft Compute Driver Model (MCDM) on the Rubin architecture. MCDM provides a compute-only driver model, while Tesla Compute Cluster (TCC) is not supported on Rubin and later GPUs. NVIDIA says applications and deployment tools that assume TCC should use WDDM or MCDM for their target system.
Locality domains and MPS add scheduling choices
Applications can choose between uniform streaming multiprocessor (SM) partitions across locality domains and partitions that include all available SMs. The new cudaDevSmResourceGroupLocalityDomainSupplementalSms flag, used with cudaDevSmResourceGroupLocalityDomainId, includes additional SMs in selected domains. Applications can use discovery mode in cudaDevSmResourceSplit() to obtain each partition’s SM count and distribute work accordingly.
NVIDIA Multi-Process Service (MPS) v3 adds weighted timeslicing, which lets operators set a base timeslice and scale it for each MPS server. Its SM partition load balancing lets workloads borrow capacity beyond their base partition when resources are available, while partitions can lend SMs when they have no attached clients. MPS reclaims borrowed resources before reassigning them, and applications continue to see a stable base partition size.
MPS v3 also supports cgroup-based routing: a cgroup v2 subtree can map to an MPS namespace, routing clients that connect through the daemon’s main socket. Per-namespace SM partition assignments apply a selected partition to every client routed to that namespace. For memory accounting, MPS can poll current usage and limits during eviction decisions when cgroup threshold notifications are missing or unreliable.
CUDA Tile moves communication into kernels
CUDA 13.5 adds multi-GPU communication directly within CUDA Tile kernels. Unicast pointers let a kernel access memory on another NVLink-connected GPU; multicast pointers and multimem operations support reductions and stores across multiple GPUs on NVIDIA NVSwitch fabrics with NVIDIA NVLink SHARP support. Applications prepare shared-memory mappings before launch, then combine communication and computation inside the kernel.
A public preview also lets CUDA Tile kernels call device functions from SIMT libraries. The supported libraries include NVIDIA NVSHMEM, NVIDIA CCCL Coop, NVIDIA Warp and NVIDIA MathDx, which covers cuFFTDx, cuBLASDx, cuSolverDx and nvCOMPDx. In this preview, Tile-SIMT interoperability covers library functions; calling developers’ own __device__ functions from Tile code is planned for a future release.
Python and CCCL updates target reusable GPU work
The CUDA Python core library cuda.core 1.2 adds batched memory copies through copy_batch(), Programmatic Dependent Launch through LaunchConfig, simpler runtime compilation and more flexible CUDA Graph updates. On GPUs with compute capability 9.0 or newer, cooperating kernels can overlap execution within the same CUDA stream through Programmatic Dependent Launch. Applications can update supported executable graph nodes, including kernel parameters and memory copies, without reinstantiating the graph.
CUDA Toolkit 13.5 includes CCCL 3.5, which adds public tuning policies for CUB device-wide algorithms. The release also adds cub::DeviceBatchedTopK, which selects the smallest or largest K items independently across segments and supports keys or key-value pairs, variable segment sizes and K values that vary by segment. NVIDIA says CUB’s batched Top-K is integrated into FlashInfer, a library of GPU kernels for LLM inference.
cub::DeviceScan adds run-to-run reproducibility for floating-point summation, producing repeatable results on the same GPU with the same input and build configuration. CUB reductions can also consume an element count stored in device-accessible memory through cuda::args::deferred. NVIDIA says this lets a reduction use a count produced by a preceding operation without transferring it to the host.
Profiling and math library changes
CUDA Toolkit 13.5 introduces a public preview of the NVIDIA Nsight Perf SDK for AI, which preserves selected GPU and CPU performance metrics and execution context from long-running training and inference workloads. Developers can explore the collected data in Perfetto. NVIDIA Nsight Compute 2026.4 adds a timeline page for time-resolved profiling data, with function statistics available in the same view.
CUDA-GDB can stop execution on CUDA Driver log events, with rules to filter events by thread, severity or message pattern. CUDA 13.5 also supports GPU core dump generation while CUPTI tracing is enabled. For Vera Rubin, NVIDIA says updated cuBLAS heuristics and kernel tuning improve out-of-the-box NVFP4 and MXFP8 matrix multiplication performance, including mixture-of-experts LLM training shapes.