Skip to content
AI.info

Deep architectures

External Memory and Memory-Augmented Networks

Explain differentiable read–write memory, memory tokens, recurrent memory, retrieval interfaces, addressing, persistence, and failure modes in memory-augmented architectures.

By the end you can

Comparison

The word memory hides several different mechanisms

Each mechanism has a different lifetime, capacity, update rule, and governance boundary.

The second row has a measured version. Transformer-XL caches the hidden states of earlier segments and lets the next segment read them. The architecture “consists of a segment-level recurrence mechanism and a novel positional encoding scheme”. That was reported at ACL in 2019, by Dai, Yang and four co-authors. The cached states buy range. The model “learns dependency that is 80% longer than RNNs and 450% longer than vanilla Transformers”. They buy speed too: it is “up to 1,800+ times faster than vanilla Transformers during evaluation”. Caching past states is a memory decision. It changes latency, not only quality.

The fourth row is a trade, and it prices storage against parameters. DeepMind's RETRO reads from a database instead of holding everything in its weights. The abstract states the deal: “With a 2 trillion token database, our Retrieval-Enhanced Transformer (RETRO) obtains comparable performance to GPT-3 and Jurassic-1 on the Pile, despite using 25× fewer parameters.” That was 2022. A second lab checked it. NVIDIA reproduced RETRO in 2023, up to 9.5B parameters over a 330B-token retrieval corpus. The result held, but not everywhere: it “largely outperforms GPT on knowledge-intensive tasks, but is on par with GPT on other tasks”. A RETRO++ variant gained +8.6 exact-match on Natural Questions. Two trillion tokens of external store bought a 25× parameter reduction. The benefit landed on knowledge-intensive work, not on everything.

FigureComparison · 4 columns

Hidden state

A fixed-size vector carried through a recurrent computation.

  • Fast streaming access
  • Learned compression
  • Limited explicit addressing
  • Ends with the sequence or session

Attention context or cache

Stored representations available for direct content lookup.

  • High-fidelity recent access
  • Cost grows with stored items
  • Usually read-only during decode
  • Bounded by context policy

Differentiable memory matrix

A neural controller reads and writes soft-addressed slots.

  • Learned storage operations
  • End-to-end differentiability
  • Interference and scaling issues
  • Roles can be hard to interpret

External retrieval store

A database or index is queried through an explicit tool interface.

  • Persistent and updateable
  • Supports permissions and provenance
  • Retrieval errors are discrete
  • Not automatically end-to-end learned

Differentiable memory adds explicit read and write heads

A controller emits keys, strengths, gates, and erase or add vectors. Soft addressing turns those into weighted reads and writes over a memory matrix.

Coupling a network to an outside store has a date on it. The Neural Turing Machine arrived in 2014, from Graves and two co-authors, and the abstract opens with the entire idea: “We extend the capabilities of neural networks by coupling them to external memory resources, which they can interact with by attentional processes.” The controller reaches that memory through attentional read and write processes. The whole system is differentiable end to end.

Content-based addressing finds similar slots. Location-based mechanisms can shift or iterate through memory. The architecture learns an algorithmic access policy rather than compressing everything into one hidden state. Learning that policy turned out to be hard to reproduce. The existing open-source NTM implementations “are unstable during training and/or fail to replicate the reported performance of NTMs”, Collier and Beel found four years later. What helped was not more memory but how the memory started. Contents initialised to small constant values “converge on average 2 times faster than the next best memory contents initialization scheme”. A differentiable store hands you a capability and an optimisation problem in the same package.

Memory augmentation changes the model from state compression to learned storage and addressing.

Visual

A neural read–compute–write cycle

Repeated access can support copying, sorting, association, and longer algorithmic behavior.

FigureProcess · 5 steps
  1. 1

    Controller observes input

    A recurrent or feed-forward network forms a query state.

  2. 2

    Read heads address memory

    Soft weights select content from one or more slots.

  3. 3

    Controller computes

    Input, prior state, and memory reads shape the next output.

  4. 4

    Write heads modify slots

    Erase and add operations update selected locations.

  5. 5

    Cycle continues

    Later steps can revisit information written earlier.

Example

Memory appears at several architectural scales

These systems solve related access problems with different operational semantics.

  • Neural Turing Machine: a controller learns differentiable soft reads and writes over a memory matrix (2014).
  • Memory tokens: special persistent states circulate through blocks to summarize or exchange context.
  • Recurrent segment memory: prior hidden states are cached and reused when processing later sequence chunks — Transformer-XL's segment-level recurrence is the version with published numbers (ACL 2019).
  • Key–value cache: autoregressive attention retains past keys and values to avoid recomputation.
  • Retrieval-augmented model: an external index returns documents or records under product-level controls; RETRO's index held 2 trillion tokens (2022).

Case

The differentiable neural computer read and wrote an external memory matrix

The idea reached a journal two years later. A differentiable neural computer “consists of a neural network that can read from and write to an external memory matrix, analogous to the random-access memory in a conventional computer”. That description appeared in Nature in 2016, from Graves, Wayne and eighteen co-authors. The machine can “learn tasks such as finding the shortest path between specified points and inferring the missing links in randomly generated graphs”, they write, and “then generalize these tasks to specific graphs such as transport networks and family trees”. The memory here is not a metaphor. It is a matrix with addresses.

Key idea

Model memory and product memory have different safety obligations

A differentiable memory inside a forward pass usually lacks durable identity, deletion semantics, audit trails, and access control. A user-profile database needs all four.

Deletion is not a design preference. It has an article number. Article 17(1) of the GDPR reads: “The data subject shall have the right to obtain from the controller the erasure of personal data concerning him or her without undue delay and the controller shall have the obligation to erase personal data without undue delay where one of the following grounds applies:” Six enumerated grounds follow. Article 5(1)(e) adds that personal data must be kept in identifiable form no longer than necessary. A store whose records you cannot name is a store you cannot erase from on request.

There is an obvious escape. The information is spread through the weights, so it is no longer personal data. That escape has already been narrowed. Opinion 28/2024 of the European Data Protection Board holds that “AI models trained with personal data cannot, in all cases, be considered anonymous”. A model counts as anonymous only where two likelihoods are both insignificant: direct extraction of personal data, and obtaining it from queries.

Do not implement regulated or personal persistence by merely extending hidden context. Use explicit stores with authorization, provenance, retention, and user controls.

A learnable memory mechanism is not automatically an acceptable persistence system.

Steps

Stress a memory architecture deliberately

Accuracy on short examples can hide overwrite and addressing failures.

Step five is the one that has already failed in public. Ask a language model enough of the right questions and it will hand back pieces of its training data. “This paper demonstrates that in such settings, an adversary can perform a training data extraction attack to recover individual training examples by querying the language model,” Carlini, Tramèr and ten co-authors told the USENIX Security Symposium in 2021. The demonstration was manual. They took 1,800 candidate sequences generated by GPT-2 and inspected them by hand. The resulting set was validated against GPT-2's training data through the model's original authors. Of the 1,800 candidates, 604 were unique memorised training examples — an aggregate true-positive rate of 33.5%. Seventy-eight of them were examples of individuals' names, phone numbers, addresses and social-media accounts. Larger models were more vulnerable than smaller ones. Scaling the store scales the exposure.

That failure now has a catalogue entry. NIST's 2025 taxonomy of adversarial machine learning lists Data Extraction as identifier NISTAML.038, inside the Privacy Compromises class NISTAML.03. It extends the exposure explicitly to “sensitive information in RETRIEVAL-AUGMENTED GENERATION (RAG) databases provided in-context”. A permissions audit that checks only the retrieval filter has checked one of the two doors.

FigureProcess · 5 steps
  1. 1. Extend delay

    Increase the gap between write and required read beyond training lengths.

  2. 2. Add interference

    Insert similar and irrelevant records between storage and retrieval.

  3. 3. Test update semantics

    Overwrite, correct, append, and delete items while tracking stale reads.

  4. 4. Separate capacity from policy

    Increase slots and compare whether the controller uses them effectively.

  5. 5. Audit permissions

    Verify that one user, tenant, or task cannot retrieve another’s records.

Analogy

A worker with scratch paper, filing cabinets, and a library

A worker keeps a thought in mind, writes temporary notes, stores labeled folders, and requests books from a library. Each store differs in speed, capacity, permanence, and authorization.

A folder has a label and a shelf. Neural addresses are soft vectors, and learned stores can entangle records. One word, memory, should not erase distinct interfaces.

Memory architecture begins by specifying lifetime, address method, write authority, and evidence fidelity.

Explicit memory does not eliminate reasoning bottlenecks

A store may preserve exact records. The controller must still formulate useful queries, combine retrieved evidence, and decide what to write. Access operations can become the new source of error.

Two measurements separate the capacity advertised from the capacity actually usable. The first one is about position. Where a needed record sits inside a long context decides whether the model uses it. On multi-document QA and on key–value retrieval, Liu, Lin and five co-authors reported in 2024: “In particular, we observe that performance is often highest when relevant information occurs at the beginning or end of the input context, and significantly degrades when models must access relevant information in the middle of long contexts, even for explicitly long-context models.” The record was present in every one of those trials. Position alone decided whether it was used.

The second measurement counts models rather than positions. NVIDIA's RULER benchmark evaluated 17 long-context models on 13 tasks in 2024. All of them claim context sizes of 32K tokens or greater. And yet “only half of them can maintain satisfactory performance at the length of 32K”.

Measure write precision, read recall, stale-memory rate, interference, and end-task benefit. More slots do not fix a controller that addresses them poorly. Half of an advertised 32K is a capacity the access policy never delivered.

Capacity, addressing, and reasoning quality are separate constraints.

Key takeaways