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Senior ASIC RTL Design Engineer, AI Hardware

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference serv

Company

Cerebras

Location

Sunnyvale, CA

Status

Open

Posted

2026-09-24T21:22:09.918+00:00

Cerebras seeks a senior front-end design engineer for the next generations of its Wafer Scale Engine, the company's AI chip. Work covers functional specification, micro-architecture, RTL development and synthesis, and collaboration with physical design, verification and DFT teams. The posting asks for a master's degree, eight or more years of high-performance RTL design, front-end chip and third-party IP integration, and TCP/IP, RDMA, Ethernet, PCIe and Serdes knowledge. Base pay is $200,000 to $290,000, and the role is open to remote despite the hybrid listing.