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RTL Design Engineer, Machine Learning Accelerators

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part

Company

Google

Location

Sunnyvale, CA, USA

Status

Open

Posted

2026-08-21T16:08:28+00:00

Google is hiring an RTL design engineer on its AI and Infrastructure team in Sunnyvale, working on TPU silicon that runs AI/ML workloads. The role involves designing and documenting blocks of an ASIC, including functionality and timing, proposing design improvements, and coordinating with software teams on interfaces. Requirements: a bachelor's degree in electrical or computer engineering or computer science, four years of custom silicon design, and Verilog or SystemVerilog experience. Preferred: a master's or PhD in computer architecture, Python or Perl scripting, and knowledge of accelerators or memory hierarchies.