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Lead RTL Design Engineer

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference serv

Company

Cerebras

Location

Sunnyvale, CA

Status

Open

Posted

2026-08-07T21:00:18.824+00:00

Cerebras is hiring a lead front-end design engineer to work on the next generations of its Wafer Scale Engine, the chip behind its AI training and inference systems. The job covers functional specification, micro-architecture, RTL development and synthesis, managing an external ASIC vendor, and working with physical design, verification, DFT, software and system teams through bring-up. Requirements include a master's degree, 8–15 years of complex RTL work, high-speed IO and networking experience (TCP/IP, RDMA, Ethernet, PCIe, Serdes), plus Python or TCL scripting. Vendor management and silicon-level debug set it apart.